Low parasitic capacitance bit line process for stack DRAM

A method of manufacturing low parasitic capacitance bit line for stack dynamic random access memory (DRAM), comprising:

• offering a semi-conductor base, which semi-conductor base having an oxide, plural word line stacks, plural bit line stacks and plural polysilicons, which oxide being placed on the plural word line stacks and on the plural polysilicons not stacked with the plural bit line stacks thereon;
• applying a multi layer resist coat onto the upper surface of the semiconductor base;
• removing the multi layer resist coat to form holes, and further removing the part of the oxide located over the plural polysilicons in the hole to form contact holes exposing the polysilicons;
• depositing an oxide layer;
• etching the oxide layer to form plural oxide layer spacers;
• depositing a polysilicon layer;
• performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer which is column-shaped to form capacitor contacts;
• and
• using another oxide to fill into a space among the word line stacks and the capacitor contacts.