ESD improvement with dynamic substrate resistance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorDa-Wei Lai
Life of this patent
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Abstract
In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.
Claims19
An electrostatic discharge (ESD) protection circuit, comprising:
- a first NMOS transistor having a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source, the first voltage source set at ground potential;
- and
- a substrate resistance control circuit coupled to a body of the first NMOS transistor, the substrate resistance control circuit including:
- a second NMOS transistor having a drain directly coupled to a first P+diffusion region of the first NMOS transistor, a gate coupled to an RC circuit, and a source coupled to the first voltage source, the substrate resistance control circuit for increasing a resistance of the body of the first NMOS transistor during an ESD event.
An electrostatic discharge (ESD) protection circuit, comprising:
- a first NMOS transistor having a gate coupled to ground through a first resistor, a drain coupled to a input/output (I/O) pad, and a source coupled to ground;
- and
- a substrate resistance control circuit coupled to a body of the first NMOS transistor for increasing a resistance of the body of the first NMOS transistor during an ESD event, the substrate resistance control circuit including:
- a second NMOS transistor having a drain directly coupled to first and second P+diffusion regions of the first NMOS transistor, a first N+diffusion region of the second NMOS transistor coupled to ground;
- and
- an RC circuit coupled to a gate of the second NMOS transistor.
An electrostatic discharge (ESD) protection circuit, comprising:
- a first NMOS transistor having a gate coupled to ground, a drain coupled to a input/output (I/O) pad, and a source coupled to ground;
- and
- a substrate resistance control circuit coupled to a body of the first NMOS transistor for increasing a resistance of the body of the first NMOS transistor during an ESD event, the substrate resistance control circuit including:
- a second NMOS transistor having a drain directly coupled to first and second P+diffusions regions of the first NMOS transistor, a source of the second NMOS transistor coupled to a body of the second NMOS transistor and to ground;
- a first resistor coupled to a first voltage source and to a first node, the first voltage source having a higher voltage potential than ground, and
- a capacitor coupled to the first node and to ground.
Dependencies are inferred from the claim text.