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US 8,008,705 B2Granted
Semiconductor storage device and method of manufacturing same
AssigneeRenesas Electronics Corporation
InventorKohji Kanamori
Life of this patent
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Abstract
Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.
Claims18
A semiconductor storage device comprising:
- a plurality of first-conductivity-type diffusion regions extending in parallel with one another along one direction on a surface of a well of a second conductivity type;
- a gate electrode extending along the one direction and being disposed on a substrate via a substrate insulating film between two mutually adjacent ones of said plurality of first-conductivity-type diffusion regions;
- and
- a word line extending along a direction perpendicular to said one direction and three-dimensionally intersecting said gate electrode,
- wherein an area of the well not covered by said gate electrode and said word line has a trench surrounding one of the plurality of first-conductivity-type diffusion regions within the area a trench insulating film being buried in said trench, and
- wherein said trench is formed between said one of the plurality of first-conductivity-type diffusion regions and said gate electrode such that said one of the plurality of first conductivity-type diffusion regions and said gate electrode respectively contact opposing surfaces of sidewalls of said trench.
3 more elements
A semiconductor storage device, comprising:
- a plurality of first-conductivity-type diffusion regions extending in parallel with one another along one direction on a surface of a well of a second conductivity type;
- a gate electrode extending along the one direction and being disposed on a substrate via a substrate insulating film between two mutually adjacent ones of said plurality of first-conductivity-type diffusion regions;
- and
- a word line extending along a direction perpendicular to said one direction and three-dimensionally intersecting said gate electrode,
- wherein an area of the well not covered by said gate electrode and said word line has a trench surrounding one of the plurality of first-conductivity-type diffusion regions within the area, a trench insulating film being buried in said trench,
- wherein said trench is formed between said one of the plurality of first-conductivity-type diffusion regions and said gate electrode such that said one of the plurality of first conductivity-type diffusion regions and said gate electrode contact a sidewall of said trench,
- wherein said gate electrode and said substrate insulating film comprise a select gate,
- wherein, at an intersection of said word line and said select gate, on a side wall of said select gate, a floating gate is provided, and said word line is provided on said select gate and said floating gate via a word line insulating film,
- wherein a surface of said substrate has a common diffusion region of a first conductivity type disposed along a direction perpendicular to said one direction at a position spaced away from at least one longitudinal end of said plurality of first-conductivity-type diffusion regions,
- wherein said plurality of first-conductivity-type diffusion regions arc connected to corresponding ones of bit tines arranged in a metal interconnect layer by contacts,
- wherein said select gate intersects said common diffusion region via a common insulating film, and
- wherein said select gate protrudes beyond a side edge of said common diffusion region.
9 more elements
Dependencies are inferred from the claim text.