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US 8,008,645 B2Granted
Memory cell array with low resistance common source and high current drivability
AssigneeSpansion LLC
InventorMasao Taguchi
Life of this patent
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Abstract
In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.
Claims12
A semiconductor device comprising:
- a substrate;
- a first plurality of spaced-apart source regions in the substrate, the first plurality of spaced-apart source regions arranged in a first column of individual source regions;
- a second plurality of spaced-apart source regions in the substrate, the second plurality of spaced-apart source regions arranged in a second column of individual source regions, wherein each source region of the first and second pluralities of spaced-apart source regions comprises only a single layer;
- a first elongated conductor positioned on the substrate and connecting the first plurality of spaced-apart source regions, such that the first plurality of spaced-apart source regions form a first common source;
- and
- a second elongated conductor positioned on the substrate and connecting the second plurality of spaced-apart source regions, such that the second plurality of spaced-apart source regions form a second common source.
3 more elements
Dependencies are inferred from the claim text.