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US 8,007,914 B2Granted
Two layer LTO temperature oxide backside seal for a wafer
AssigneeSiltronic AG
InventorsJin-Xing Li, Boon-Koon Ow
Life of this patent
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Abstract
A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.
Claims3
A wafer having a two layer backside seal, comprising:
- a silicon wafer substrate having a first major side and second major side and a two layer backside seal comprising;
- a low stress LPPECVD- low temperature oxide (LTO) layer having a first major side and a second major side, the first major side of the low stress LPPECVD-LTO layer in direct contact with the first major side of the wafer substrate;
- and
- a high stress LPPECVD-LTO layer having a first major side and a second major side, the first major side of the high stress LPPECVD-LTO layer being adjacent to the second major side of the low stress LPPECVD-LTO layer;
- and
- wherein the stress in the low stress LPPECVD-LTO layer is less than 100 MPa and the stress in the high stress LPPECVD-LTO layer is less than 300 MPa and the stress in the high stress LPPECVD-LTO layer is higher than the stress in the low stress LPPECVD-LTO layer.
3 more elements
Dependencies are inferred from the claim text.