Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor

A double data rate (DDR) counter, comprising:

• a first stage for generating a least significant bit (LSB) of a plurality of bits of the counter, the first stage having a first clock input and being edge-triggered on one of a rising edge and a falling edge of a signal applied at the first clock input;
• at least one second stage for generating another bit of the plurality of bits of the counter, the at least one second stage having a second clock input and being edge-triggered on the other of a rising edge and a falling edge of a signal applied at the second clock input;
• and
• a logic circuit for performing a logical operation on an output of the first stage and an output of the second stage to generate the LSB of the plurality of bits.

A double data rate (DDR) counter, comprising:

• a first stage for generating a least significant bit (LSB) of a plurality of bits of the counter, the first stage having a first clock input and being edge-triggered on one of a rising edge and a falling edge of a signal applied at the first clock input;
• at least one second stage for generating another bit of the plurality of bits of the counter, the at least one second stage having a second clock input and being edge-triggered on the other of a rising edge and a falling edge of a signal at the second clock input;
• and
• a count stop circuit for stopping counting of the counter, wherein the count stop circuit comprises a multiplexer for selecting one of the positive and negative outputs of the second stage to be used in generating the LSB of the plurality of bits.

An analog-to-digital converter (ADC) using correlated double sampling, the ADC comprising:

• an input for receiving an input signal;
• and
• a double data rata (DDR) counter comprising:
• a first stage for generating a least significant bit (LSB) of a plurality of bits of the counter, the first stage having a first clock input and being edge-triggered on one of a rising edge and a falling edge of a signal applied at the first clock input;
• and
• at least one second stage for generating another bit of the plurality of bits of the counter, the at least one second stage having a second clock input and being edge-triggered on the other of a rising edge and a falling edge of a signal applied at the second clock input;
• wherein
• a value in the DDR counter is related to an analog-to-digital conversion of the input signal,
• wherein the counter further comprises a circuit for determining a value of a count in the counter and selecting one of a plurality of clock signals for a second counting process of the counter.

A CMOS image sensor, comprising:

• a pixel array;
• and
• an analog-to-digital converter (ADC) comprising a double data rate (DDR) counter, the DDR counter comprising:
• a first stage for generating a least significant bit (LSB) of a plurality of bits of the counter, the first stage having a first clock input and being edge-triggered on one of a rising edge and a falling edge of a signal applied at the first clock input;
• and
• at least one second stage for generating another bit of the plurality of bits of the counter, the at least one second stage having a second clock input and being edge-triggered on the other of a rising edge and a falling edge of a signal applied at the second clock input,
• wherein the counter further comprises a circuit for determining a value of a count in the counter and selecting one of a plurality of clock signals for a second counting process of the counter.

A method of counting in a double data rate (DDR) counter, comprising:

• generating a least significant bit (LSB) of a plurality of bits of the counter in a first stage of the counter, the first stage having a first clock input;
• generating another bit of the plurality of bits of the counter in at least one second stage of the counter, the at least one second stage having a second clock input;
• edge-triggering the first stage of the counter on one of a rising edge and a falling edge of a signal applied at the first clock input;
• edge-triggering the second stage of the counter on the other of a rising edge and a falling edge of a signal applied at the second clock input;
• and
• determining a value of a count in the counter and selecting one of a plurality of clock signals for a second counting process of the counter.