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US 7,965,113 B2Granted
System for detecting a reset condition in an electronic circuit
AssigneeCerticom Corp.
InventorJay Scott Fuller
Life of this patent
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Abstract
There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.
Claims8
A system for detecting the assertion of a reset signal, said system comprising:
- (a) a plurality of circuit elements, including an output, configurable by said reset signal to generate a string of data values at said output;
- and
- (b) a comparator, including an input, said input for receiving said string of data values and determining whether said string of data values matches a predetermined pattern;
- said comparator generating a confirmatory signal, indicative of attainment of a reset condition, if said string of data values matches said predetermined pattern.
1 more element
Dependencies are inferred from the claim text.