Tuning capacitance to enhance FET stack voltage withstand

The stacked transistor RF switch apparatus, comprising:

• a transistor stack including a plurality of constituent transistors all coupled in series connection drain to source to form a series string for which internal nodes are those between adjacent transistors, each constituent transistor having a total effective drain-source capacitance Cds and the Cds values for two constituent transistors differ from each other by at least 2%;
• and
• at least one discrete physical capacitor element Ccomp coupled between an internal node and a parasitic drain capacitance of the series string of the stack, Ccomp having an impedance that is predominantly capacitive at primary frequencies of signals ordinarily controlled by the RF switch.

A stacked transistor RF switch apparatus, comprising:

• a transistor stack including a plurality of constituent transistors all coupled in series connection drain to source to form a series string for which internal nodes are those between adjacent transistors, each constituent transistor having a total effective drain-source capacitance Cds;
• and
• a first discrete capacitive element disposed in parallel to one of at least two constituent transistors drain-source and a second discrete capacitive element disposed in parallel to another of the least two constituent transistors drain-source, the at least two constituent transistors Cds values differing from each other by at least 2%.

A method of fabricating a stacked RF switch that includes a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising a step of establishing total effective drain-source capacitance Cds values that are significantly different for different transistors in the stack, wherein:

• a) such difference is at least 2% between a maximum Cds value and a minimum Cds value of the constituent transistors of the stacks;
• or
• b) for at least half of adjacent transistor pairs, a difference between Cds values of each pair differs by an amount greater than a total Cpd of an internal node between such pair, where the total Cpd of a node is a sum of all parasitic capacitance elements coupled to the node that are not part of a Cds.