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US 7,932,888 B2Granted
Pulse output circuit, shift register, and display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHiroyuki Miyake
Life of this patent
Estimating the term…
Abstract
An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.
Claims24
A pulse output circuit comprising:
- first to ninth transistors;
- first to sixth input terminals;
- and
- an output terminal,
- wherein the pulse output circuit is electrically connected to first to fifth power supply lines,
- wherein a first electrode of the first transistor is electrically connected to the first power supply line, a second electrode of the first transistor is electrically connected to a gate electrode of the third transistor, and a gate electrode of the first transistor is electrically connected to the fourth input terminal,
- wherein a first electrode of the second transistor is electrically connected to the second power supply line, a second electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and a gate electrode of the second transistor is electrically connected to a gate electrode of the fourth transistor,
- wherein a first electrode of the third transistor is electrically connected to the first input terminal and a second electrode of the third transistor is electrically connected to the output terminal,
- wherein a first electrode of the fourth transistor is electrically connected to the third power supply line and a second electrode of the fourth transistor is electrically connected to the output terminal,
- wherein a first electrode of the fifth transistor is electrically connected to the fourth power supply line, a second electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the fifth transistor is electrically connected to the fourth input terminal,
- wherein a first electrode of the sixth transistor is electrically connected to the fourth power supply line, a second electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the sixth transistor is electrically connected to the fifth input terminal,
- wherein a first electrode of the seventh transistor is electrically connected to the fifth power supply line, a second electrode of the seventh transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the seventh transistor is electrically connected to the sixth input terminal,
- wherein a first electrode of the eighth transistor is electrically connected to the fifth power supply line, a second electrode of the eighth transistor is electrically connected to a second electrode of the ninth transistor, and a gate electrode of the eighth transistor is electrically connected to the second input terminal, and
- wherein a first electrode of the ninth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the ninth transistor is electrically connected to the third input terminal.
11 more elements
A pulse output circuit comprising:
- first to ninth transistors;
- a first capacitor;
- first to sixth input terminals;
- and
- an output terminal,
- wherein the pulse output circuit is electrically connected to first to sixth power supply lines,
- wherein a first electrode of the first transistor is electrically connected to the first power supply line, a second electrode of the first transistor is electrically connected to a gate electrode of the third transistor, and a gate electrode of the first transistor is electrically connected to the fourth input terminal,
- wherein a first electrode of the second transistor is electrically connected to the second power supply line, a second electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and a gate electrode of the second transistor is electrically connected to a gate electrode of the fourth transistor,
- wherein a first electrode of the third transistor is electrically connected to the first input terminal and a second electrode of the third transistor is electrically connected to the output terminal,
- wherein a first electrode of the fourth transistor is electrically connected to the third power supply line and a second electrode of the fourth transistor is electrically connected to the output terminal,
- wherein a first electrode of the fifth transistor is electrically connected to the fourth power supply line, a second electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the fifth transistor is electrically connected to the fourth input terminal,
- wherein a first electrode of the sixth transistor is electrically connected to the fourth power supply line, a second electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the sixth transistor is electrically connected to the fifth input terminal,
- wherein a first electrode of the seventh transistor is electrically connected to the fifth power supply line, a second electrode of the seventh transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the seventh transistor is electrically connected to the sixth input terminal,
- wherein a first electrode of the eighth transistor is electrically connected to the fifth power supply line, a second electrode of the eighth transistor is electrically connected to a second electrode of the ninth transistor, and a gate electrode of the eighth transistor is electrically connected to the second input terminal,
- wherein a first electrode of the ninth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the ninth transistor is electrically connected to the third input terminal, and
- wherein a first electrode of the first capacitor is electrically connected to the sixth power supply line, and a second electrode of the first capacitor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor.
13 more elements
A shift register comprising:
- a plurality of pulse output circuits comprising a (m−2)th pulse output circuit, a (m−1)th pulse output circuit, an m-th pulse output circuit, a (m+1)th pulse output circuit, and a (m+2)th pulse output circuit (m≧3);
- and
- first to fourth signal lines each of which is configured to output a clock signal,
- wherein each of the pulse output circuits comprises first to sixth input terminals and an output terminal,
- wherein the first to third input terminals of the m-th pulse output circuit are electrically connected to three different signal lines among the first to fourth signal lines,
- wherein the fourth input terminal of the m-th pulse output circuit is electrically connected to the output terminal of the (m−2)th pulse output circuit,
- wherein the fifth input terminal of the m-th pulse output circuit is electrically connected to the output terminal of the (m−1)th pulse output circuit,
- wherein the sixth input terminal of the m-th pulse output circuit is electrically connected to the output terminal of the (m+2)th pulse output circuit, and
- wherein the output terminal of the m-th pulse output circuit is electrically connected to the sixth input terminal of the (m−2)th pulse output circuit, the fifth input terminal of the (m+1)th pulse output circuit, and the fourth input terminal of the (m+2)th pulse output circuit.
6 more elements
A display device comprising:
- a pixel;
- and
- a shift register configured to drive the pixel,
- herein the shift register comprises:
- a plurality of pulse output circuits comprising a (m−2)th pulse output circuit, a (m−1)th pulse output circuit, an m-th pulse output circuit, a (m+1)th pulse output circuit, and a (m+2)th pulse output circuit (m≧3);
- and
- first to fourth signal lines each of which is configured to output a clock signal,
- wherein each of the pulse output circuits comprises first to sixth input terminals and an output terminal,
- wherein the first to third input terminals of the m-th pulse output circuit are electrically connected to three different signal lines among the first to fourth signal lines,
- wherein the fourth input terminal of the m-th pulse output circuit is electrically connected to the output terminal of the (m−2)th pulse output circuit,
- wherein the fifth input terminal of the m-th pulse output circuit is electrically connected to the output terminal of the (m−1)th pulse output circuit,
- wherein the sixth input terminal of the m-th pulse output circuit is electrically connected to the output terminal of the (m+2)th pulse output circuit, and
- wherein the output terminal of the m-th pulse output circuit is electrically connected to the sixth input terminal of the (m−2)th pulse output circuit, the fifth input terminal of the (m+1)th pulse output circuit, and the fourth input terminal of the (m+2)th pulse output circuit.
10 more elements
Dependencies are inferred from the claim text.