Variable fill and cheese for mitigation of BEOL topography
AssigneeInternational Business Machines Corporation
InventorsTodd C Bailey, Ryan P. Deschner, Wai-Kin Li, Roger A. Quon
Life of this patent
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Abstract
A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached.
Claims16
A method of designing features on a semiconductor wafer comprising:
- providing a semiconductor wafer;
- providing a design of active or functional features of different frequencies for chiplets to be formed on the wafer;
- determining pattern density of the active or functional features on the chiplets while filtering out high frequency active or functional features to desensitize the determined active or functional pattern density to the high frequency features;
- applying a pattern of spaced dummy features on an area of at least one chiplet not covered by active or functional features;
- and
- uniformly expanding or reducing size of the dummy features until a desired pattern density of the dummy features in the area is reached, matching the desensitized active or functional pattern density.
A method of designing features on a semiconductor wafer comprising:
- providing a semiconductor wafer;
- providing a design of active or functional features for a plurality of chiplets to be formed on the wafer, the chiplets being arranged in an exposure field in a desired spaced layout and separated by kerf areas having different pattern densities of the active or functional features;
- determining pattern density of the active or functional features on each of the chiplets;
- determining the chiplet having the highest pattern density of the active or functional features;
- applying a pattern of spaced dummy features on an area of at least one chiplet areas of the chiplets not covered by active or functional features;
- and
- uniformly expanding or reducing size of the dummy features until pattern density of the dummy features substantially matches the pattern density of the chiplet having the highest pattern density of the active or functional features.
A method of designing features on a semiconductor wafer comprising:
- providing a semiconductor wafer oriented along an x- and y-direction;
- providing a design of active or functional features for chiplets to be formed on the wafer, the active or functional features having a substantially constant density in the y-direction on the wafer and a varying density, from a lower density to a higher density, in the x-direction;
- determining pattern density of the active or functional features on the chiplets;
- applying a pattern of spaced dummy features on an area of at least one chiplet not covered by active or functional features;
- and
- uniformly expanding or reducing size of the dummy features until pattern density of the dummy features have a substantially constant density in the y-direction on the wafer and a varying density, from a lower density to a higher density, in the x-direction, substantially matching the pattern density of the active or functional features.
Dependencies are inferred from the claim text.