Semiconductor device having saddle fin-shaped channel and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising the steps of:

• forming an isolation layer on a semiconductor substrate to delimit active regions;
• etching the active regions and the isolation layer to define recesses having a first depth;
• etching the recesses having the first depth that are defined in the isolation layer to form recesses having a second depth such that recess patterns for gates having a first depth in the active region and a second depth in the isolation layer are defined;
• enlarging a width of upper parts of the recess patterns for gates defined in the isolation layer;
• forming gate patterns in and over the recess patterns for gates, the respective gate patterns having a width less than that of the enlarged upper part of the respective recess patterns in the isolation layer such that gaps are created at least between the gate patterns and the enlarged upper parts of the recess patterns for gates defined in the isolation layer;
• and
• forming a gate spacer to cover the gate patterns and to fill the gaps.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming an isolation layer on a semiconductor substrate to delimit active regions;
• etching the active regions and the isolation layer using sacrificial layer patterns and hard mask patterns to define recess patterns for gates;
• forming gate patterns in and over the recess patterns for gates;
• and
• forming a gate spacer to cover the gate patterns,
• wherein the step of defining the recess patterns for gates comprises the steps of:
• etching the active regions and the isolation layer to define recesses having a first depth using the hard mask patterns;
• and
• etching the recesses having the first depth in the isolation layer to form recesses having a second depth in the isolation layer through a blanket etching process using the sacrificial layer patterns while simultaneously enlarging a width of upper parts of the recess patterns for gates,
• wherein the gate patterns are formed to have a width less than that of the enlarged upper parts of the recess patterns for gates such that gaps are created at least between the gate patterns and the enlarged upper parts of the recess patterns for gates defined in the isolation layer, and
• wherein the gate spacer fills the gaps between the gate patterns and the enlarged upper parts of the recess patterns for gates defined in the isolation layer.