Controlling warping in integrated circuit devices
AssigneeAgere Systems Inc.
InventorsJohn W. Osenbach, Thomas H. Shilling, Weidong Xie
Life of this patent
Estimating the term…
Abstract
Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.
Claims12
A method of controlling warping of a power transistor method comprising at least one die attached to a base, the method comprising the step of:
- applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die;
- and
- varying one or more of composition and thickness of the counterbalancing layer to affect thermal expansion properties of the counterbalancing layer, wherein said counterbalancing layer comprises at least one metal having a lower coefficient of thermal expansion than a coefficient of thermal expansion of said base.
Dependencies are inferred from the claim text.