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US 7,923,340 B2Granted
Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
AssigneeAgere Systems Inc.
InventorsAlan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Abstract
The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
Claims18
A method of manufacturing a semiconductor device, comprising:
- forming openings in a first implant mask located over a bipolar region and a first non-bipolar region of a semiconductor substrate to expose a bipolar region portion and the first non-bipolar region;
- conducting a first implant through the openings to place a dopant in the semiconductor substrate to form tubs in the bipolar region portion and tubs in the first non-bipolar region;
- forming openings in a second implant mask located over the bipolar region portion and a second non-bipolar region to expose the tubs in the bipolar region portion and expose the second non-bipolar region, wherein the tubs of the bipolar region are collector contact tubs for bipolar transistors and the tubs of the first non-bipolar region being protected by the second implant mask;
- and
- conducting a second implant through the openings to place the dopant in the tubs in the bipolar region and form tubs in the second non-bipolar region, such that the dopant concentration in the tubs of the bipolar region is greater than the dopant concentration in the tubs of the second non-bipolar region.
2 more elements
A semiconductor device, comprising:
- a bipolar transistor region, including collector contact tubs located in a semiconductor substrate, the collector contact tubs each having a dopant concentration ranging from about 1E17 atoms/cm3 to about 6E18 atoms/cm3, and wherein the depth of the dopant concentrations ranges from about 0 nm to about 1000 nm;
- and
- an non-bipolar transistor region, including transistor tubs located in a semiconductor substrate, source/drains located in each of the transistor tubs, and a gate electrode located over each of the transistor tubs, the transistor tubs having a dopant concentration within the depth range that is less than the collector contact tubs, wherein the vertical bipolar transistors are PNP or NPN vertical bipolar transistors and the transistor tubs are NMOS or CMOS transistor tubs, respectively.
A method of manufacturing a semiconductor device, comprising:
- forming openings in a first implant mask located over a vertical bipolar transistor region and a first NMOS or CMOS transistor region of a semiconductor substrate to expose a portion of the vertical transistor bipolar region and the first NMOS or CMOS transistor region;
- conducting a first implant through the openings to place a dopant in the semiconductor substrate to form tubs in the portion of the vertical bipolar transistor region and the first NMOS or CMOS transistor region;
- forming openings in a second implant mask located over the vertical bipolar transistor region and a second NMOS or CMOS transistor region to expose the tubs in the vertical bipolar transistor region and the second NMOS or CMOS transistor region;
- and
- conducting a second implant through the openings to place the dopant in the tubs of the vertical bipolar transistor region and form tubs in the second NMOS or CMOS transistor region, such that the dopant concentration in the tubs of the vertical bipolar transistor region is greater than the dopant concentration in the tubs of the second NMOS or CMOS transistor region.
2 more elements
Dependencies are inferred from the claim text.