Design methodology for MuGFET ESD protection devices

A method for manufacturing a multi-gate field-effect transistor (MuGFET) electrostatic discharge (ESD) protection device having a given layout by means of a given manufacturing process, comprising:

• selecting multiple combinations of possible layout and process parameter values including at least fin width, gate length, and number of fins, each of said combinations being selected to meet predetermined ESD constraints for said MuGFET ESD protection device,
• determining multiple values for at least one other parameter having a predetermined relationship with said fin width, gate length, and number of fins,
• determining for said at least one other parameter an optimum value in view of a predetermined design target apart from said predetermined ESD constraints,
• determining parameter values for said fin width, gate length, and number of fins substantially on the basis of the optimum value determined of the one other parameter, and
• manufacturing said MuGFET ESD protection device substantially using said optimum value of the at least one other parameter and the determined parameter values for fin width, gate length, and number of fins.