Testing an embedded core
AssigneeXilinx, Inc.
InventorsAdarsh Pavle, Shahin Toutounchi
Life of this patent
Estimating the term…
Abstract
A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.
Claims19
A method for testing an integrated circuit having a hardwired embedded core and memory, the memory being coupled to the embedded core in the integrated circuit, the method comprising:
- writing a test vector to the memory while the embedded core is operative;
- inputting the test vector from the memory to the embedded core to mimic scan chain input to the embedded core;
- obtaining a test result from the embedded core responsive in part to the test vector input;
- loading a portion of the test vector into a shift register of a first controller;
- outputting the portion of the test vector from the shift register into a second controller for subsequent writing to the memory;
- and
- wherein the writing of the portion of the test vector is from the second controller to the memory.
A system for testing an embedded core coupled to an array of memory cells within a host integrated circuit, comprising:
- a programmed computer;
- the programmed computer programmed with a testing software program;
- a device under test coupled to the programmed computer for receiving test vectors therefrom and for providing test results thereto responsive to the test vectors;
- the device under test including:
- a write controller for respectively receiving portions of the test vectors and configured to convert each portion of the portions from serial to parallel to output parallel data;
- the write controller configured to generate control information and address information;
- a memory controller coupled to the write controller for receiving the address information, the control information, and the parallel data therefrom;
- the array of memory cells coupled to the memory controller, the memory controller for selectively writing the parallel data to locations in the array of memory cells;
- the embedded core coupled to the array of memory cells, wherein operation of the embedded core is dynamically alterable responsive to the parallel data input from the array of memory cells;
- and
- the write controller, the memory controller, and the array of memory cells configured to mimic scan chain input with respect to the testing software program for testing the embedded core.
A host integrated circuit having an embedded core and memory, the host integrated circuit comprising:
- a write controller for respectively receiving portions of test vectors;
- a memory controller coupled to the write controller for receiving address information, control information, and data from the write controller;
- the memory coupled to the memory controller for selectively writing the data thereto;
- the embedded core coupled to the memory, wherein operation of the embedded core and the memory is configured for dynamically writing to the memory while operating the embedded core;
- and
- the write controller, the memory controller, and the memory configured to mimic scan chain input with respect to a testing software program for testing the embedded core.
Dependencies are inferred from the claim text.