Storage nitride encapsulation for non-planar sonos NAND flash charge retention

A method of manufacturing a microelectronic device, comprising:

• providing a silicon substrate having a recessed trench isolation feature in a dielectric region and a silicon feature in a silicon region adjacent the dielectric region;
• forming a tunnel dielectric feature on the silicon substrate within the silicon region;
• forming a silicon-rich nitride layer on a silicon substrate;
• etching the silicon-rich nitride layer to form an opening within the dielectric region;
• etching the recessed trench isolation feature through the opening to form a gap between the silicon-rich nitride layer and the recessed trench isolation feature;
• and
• forming a first dielectric material on the silicon-rich nitride layer and sidewalls of the silicon feature.

A semiconductor device comprising:

• a recessed shallow trench isolation (STI) feature formed in a semiconductor substrate, defining a STI region and a semiconductor region;
• a tunnel oxide feature disposed on the semiconductor substrate within the semiconductor region;
• a silicon nitride layer disposed on the semiconductor substrate, overlying the tunnel oxide feature and the recessed STI feature;
• and
• a silicon oxide layer within the STI region and interposed between the recessed STI feature and the silicon nitride layer, separating the silicon nitride layer from sidewall of the semiconductor substrate.