Method to improve writer leakage in SiGe bipolar device
AssigneeAgere Systems Inc.
InventorsAlan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Abstract
The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
Claims10
A semiconductor device, comprising:
- a bipolar transistor region, including:
- a first a silicon/germanium SiGe layer located over a collector tub and having a Ge concentration and wherein a thickness of the first SiGe layer is less than 35 nm and has a strain associated therewith;
- a second grated SiGe layer located over;
- and
- a silicon capping layer over the second SiGe layer;
- and
- an emitter layer located over the silicon capping layer;
- and
- a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.
A semiconductor device, comprising:
- a bipolar transistor region, including:
- a first a silicon/germanium SiGe layer located over a collector tub and having a Ge concentration that ranges from about 5% to about 10% by weight and has a strain associated therewith;
- a second grated SiGe layer located over the first SiGe layer;
- and
- a silicon capping layer over the second SiGe layer;
- and
- an emitter layer located over the silicon capping layer;
- and
- a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.
Dependencies are inferred from the claim text.