Design structure for semiconductor on-chip repair scheme for negative bias temperature instability

A system comprising:

• a non-transitory computer readable medium with a design structure stored therein;
• and
• a machine for manufacturing a semiconductor chip comprising instructions that when executed by a computer retrieves said design structure and produces said semiconductor chip, wherein said design structure comprises:
• a substrate;
• a transistor on said substrate, wherein, due to negative bias temperature instability, said transistor is subject to performance degradation away from an optimal performance level;
• a monitor connected to said transistor and determining when a current performance level of said transistor is below a predetermined threshold performance level for said transistor;
• an interlayer dielectric material above said transistor;
• a heating element within said interlayer dielectric material, aligned vertically above said transistor and electrically isolated from said transistor by said interlayer dielectric material;
• a first wiring level within said interlayer dielectric material and above said heating element;
• a first contact electrically connecting said first wiring level to said transistor, said first contact extending vertically through said heating element and further being electrically isolated from said heating element by said interlayer dielectric material;
• and
• a pulse generator in communication with said monitor and coupled to said heating element, said pulse generator automatically applying a current with a predetermined value to said heating element when said monitor detects that said current performance level of said transistor is below said predetermined threshold performance level,
• said heating element receiving said current from said pulse generator and generating heat that raises a temperature of said transistor to a predetermined temperature, said predetermined temperature being sufficient to raise said current performance level of said transistor above said predetermined threshold performance level.