US 7,888,768 B2Granted

Power integrated circuit device having embedded high-side power switch

AssigneeFairchild Korea Semiconductor Ltd.

InventorsSung-lyong Kim, Chang-ki Jeon, Jong-jib Kim, Jong-tae Hwang

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Abstract

In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.

Claims12

Dependent claims

A power integrated circuit device, comprising:

a semiconductor substrate;
an epitaxial layer formed on the semiconductor substrate;
a first drain area formed in an upper portion of the epitaxial layer;
a first body area formed in the upper portion of the epitaxial layer apart from the first drain area;
a first gate area formed in an upper portion of the first body area;
a first source area formed in the upper portion of the epitaxial layer apart from the first body area;
a second body area having a low concentration of p-type dopant and formed in the epitaxial layer and apart from the first body area;
a buried layer having a high concentration of n-type dopant and formed between the second body area and the semiconductor substrate in a vertical direction;
a second drain area formed in an upper portion of the second body area;
a second source area formed in the upper portion of the second body area apart from the second drain area;
a gate electrode formed in an upper portion between the second drain area and the second source area;
a first metal line formed on an upper surface of the epitaxial layer and electrically connecting the first gate area to the second source area;
and
a second metal line formed on the upper surface of the epitaxial layer and electrically connecting the first source area to the second drain area.

11 more elements

Dependencies are inferred from the claim text.