Multi-fin multi-gate field effect transistor with tailored drive current

A single field effect transistor comprising:

• a substrate;
• a plurality of first semiconductor fins on said substrate, each first semiconductor fin having a first width, a first top surface and first opposing sidewalls;
• at least one second semiconductor fin on said substrate adjacent and parallel to one of said first semiconductor fins, said second semiconductor fin having a second width, a second top surface and second opposing sidewalls;
• and
• a gate traversing each of said first semiconductor fins and said second semiconductor fin, said gate comprising:
• a first section on said first top surface and on said first opposing sidewalls of each of said first semiconductor fins, said first section having a first gate length as measured parallel to said substrate and perpendicular to said first width of said first semiconductor fin;
• and
• a second section on said second top surface and said second opposing sidewalls, said second section having a second gate length as measured parallel to said substrate and perpendicular to said second width of said second semiconductor fin, said second gate length being different from said first gate length.

A field effect transistor comprising:

• a substrate;
• at least one first semiconductor fin on said substrate, said first semiconductor fin having a first top surface, first opposing sidewalls, and a first width;
• a second semiconductor fin on said substrate adjacent to said first semiconductor fin, said second semiconductor fin having a second top surface, second opposing sidewalls and a second width that is less than said first width, said first width and said second width being predetermined to minimize leakage current;
• and
• a gate traversing said first semiconductor fin and said second semiconductor fin, said gate comprising:
• a first section on said first top surface and extending vertically along said first opposing sidewalls a first distance from said first top surface towards said substrate, said first section having a first gate length as measured parallel to said substrate and perpendicular to said first width of said first semiconductor fin;
• and
• a second section on said second top surface and extending vertically along said second opposing sidewalls a second distance from said second top surface towards substrate, second distance being less than said first distance, said second section further having a second gate length as measured parallel to said substrate and perpendicular to said second width of said second semiconductor fin, said second gate length being less than said first gate length, and
• said first gate length, said second gate length, said first distance and said second distance each being predetermined to achieve a specific drive current.