US 7,888,745 B2Granted

Bipolar transistor with dual shallow trench isolation and low base resistance

AssigneeInternational Business Machines Corporation

InventorsMarwan H. Khater, Andreas D. Stricker, Bradley A. Orner, Mattias E. Dahlstrom

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Abstract

An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.

Claims22

Dependent claims

A semiconductor structure comprising:

a semiconductor substrate having at least a pair of first neighboring shallow trench isolation (STI) regions disposed therein, said pair of first neighboring STI regions defining an active area in said substrate;
a collector disposed in a buried region in said active region of said substrate, said buried region having a graded profile of dopants;
a base layer disposed atop a surface of said semiconductor substrate in said active area;
a raised extrinsic base disposed on said base layer, said raised extrinsic base having an opening to a portion of said base layer;
an emitter located in said opening and extending over a portion of said raised extrinsic base, said emitter is spaced apart and isolated from the raised extrinsic base, wherein a lower surface of the emitter is coplanar with an entire lower surface of the raised extrinsic base, and wherein the entire lower surface of the raised extrinsic base is planar;
and
a second shallow trench isolation (STI) region in said semiconductor substrate extending inward from a sidewall of each first shallow trench isolation (STI) region of the pair of said neighboring first (STI) regions, the second STI region present adjacent to each of the pair of the first neighboring STI regions and extending inwards towards said collector, wherein said second STI region does not overlie an upper surface of each of the pair of the first neighboring STI regions, and the second STI region has an inner sidewall surface in proximity to the collector that is sloped and underlying the base layer, wherein a planar surface portion of the second shallow trench isolation region is coplanar with an upper surface of the collector, and wherein said planar surface portion of the second shallow trench isolation region is parallel with a lower surface of the base layer and extends from the inner sidewall surface that is sloped towards the first trench isolation region.

4 more elements

A semiconductor structure comprising:

a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein, said pair of neighboring first STI regions defining an active area in said substrate;
a collector disposed in a buried region in said active region of said substrate, said buried region having a graded profile of dopants;
a completely monocrystalline base layer disposed atop a surface of said semiconductor substrate in said active area;
a raised extrinsic base disposed on said base layer, said raised extrinsic base having an opening to a portion of said base layer;
an emitter located in said opening and extending over a portion of said raised extrinsic base, said emitter is spaced apart and isolated from the raised extrinsic base, wherein a lower surface of the emitter is coplanar with an entire lower surface of the raised extrinsic base, and wherein the entire lower surface of the raised extrinsic base is planar;
and
a second shallow trench isolation (STI) region in said semiconductor substrate extending inward from a sidewall of each first shallow trench isolation (STI) region of the pair of said neighboring first STI regions, the second STI region present adjacent to each of the pair of the first STI regions and extending inwards towards said collector, wherein said second STI region does not overlie an upper surface of each of the pair of the first STI regions, and the second STI region has an inner sidewall surface in proximity to the collector that is sloped and underlying the base layer, wherein a planar surface portion of the second shallow trench isolation region is coplanar with an upper surface of the collector, and wherein said planar surface portion of the second shallow trench isolation region is parallel with a lower surface of the completely monocrystalline base layer and extends from the inner sidewall surface that is sloped towards the first trench region.

4 more elements

Dependencies are inferred from the claim text.