Trench capacitors and memory cells using trench capacitors

A memory cell, comprising:

• a trench capacitor in a substrate, said trench capacitor having contiguous upper, middle and lower regions, said middle region between said upper and lower regions, said lower region closed by a bottom of said trench, said trench extending from a top surface of said substrate into said substrate along an axis perpendicular to said top surface of said substrate, said axis defining a vertical direction;
• said upper region of said trench having a vertical sidewall profile;
• said middle region of said trench having a tapered sidewall profile, a width in said horizontal direction of said middle region at a juncture of said upper region and said middle region being greater than a width in said horizontal direction of said middle region at a juncture of said middle region and said lower region;
• a node dielectric layer on a bottom of said trench and on sidewalls of said trench in said lower region and on sidewalls of said trench in a lower region of said middle region, said lower region of said middle region abutting said lower region;
• a dielectric collar on sidewalls of said trench in an upper region of said middle region and on lower regions of said upper region, said dielectric collar thicker than said node dielectric layer, said upper region of said middle region abutting said lower region of said upper region;
• a first electrically conductive material filling remaining space in said lower region and said lower region of said middle region;
• a second electrically conductive material in said upper region of said middle region and said lower region of said upper region;
• a third electrically conductive material in an upper region of said upper region, said upper region of said upper region abutting said lower region of said upper region;
• and
• a field effect transistor comprising a gate electrode separated from a channel region in said substrate by a gate dielectric layer on said top surface of said substrate and first and second source/drains formed in said substrate on opposite side of said channel region, said second source/drain electrically connected to said third electrically conductive material.