High-efficiency filler cell with switchable, integrated buffer capacitance for high frequency applications

An integrated circuit chip with a top voltage supply rail and a bottom voltage supply rail, the integrated circuit chip comprising:

• a plurality of metal layers defining at least one filler cell, wherein a first field effect transistor of a first type conductivity is provided with a source electrode and a drain electrode arranged so as to act as a capacitor with respect to the bottom voltage supply rail to which one of the source electrode or the drain electrode is connected;
• and a second field effect transistor of an opposite-type conductivity to the first field effect transistor provided with a source electrode or a drain electrode, connected in series between the top voltage supply rail and a gate electrode of the first field effect transistor and with the second field effect transistor gate electrode connected to a ground potential, wherein the source or drain electrode of the first field effect transistor that is not connected to the bottom voltage supply rail is in an unconnected state.