Monitoring semiconductor device and method of manufacturing the same
AssigneeDongbu HiTek Co., Ltd.
InventorJi-Ho Hong
Life of this patent
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Abstract
Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times.
Claims13
A monitoring semiconductor device comprising:
- a plurality of polysilicon pads formed spaced apart on a semiconductor substrate;
- a plurality of N-well regions and P-well regions formed in the semiconductor substrate and between the polysilicon pads;
- active regions formed in the N-well and the P-well regions;
- a silicide layer formed on the active regions;
- and
- a polysilicon gate line electrically connecting the active regions to the polysilicon pads and configured to at least pass through the active regions a plurality of times,
- wherein the plurality of polysilicon pads comprises four, and
- wherein at least one of the polysilicon pads is connected to a current-measuring terminal of a measuring device and the other one of the polysilicon pads is connected to a voltage-measuring device.
A monitoring semiconductor device comprising:
- a plurality of polysilicon pads formed spaced apart on a semiconductor substrate;
- a plurality of N-well regions and P-well regions formed in the semiconductor substrate and between the polysilicon pads;
- active regions formed in the N-well and the P-well regions;
- a silicide layer formed on the active regions;
- and
- a polysilicon gate line electrically connecting the active regions to the polysilicon pads and configured to at least pass through the active regions a plurality of times,
- wherein the plurality of polysilicon pads comprises four,
- wherein a first pair of the polysilicon pads are connected to each other and a second pair of polysilicon pads are connected to each other, and
- wherein at least one of the polysilicon pads is connected to a current-measuring terminal of a measuring device and the other one of the polysilicon pads is connected to a voltage-measuring device.
A monitoring semiconductor device comprising:
- a plurality of polysilicon pads formed spaced apart on a semiconductor substrate;
- a plurality of N-well regions and P-well regions formed in the semiconductor substrate and between the polysilicon pads;
- active regions formed in the N-well and the P-well regions;
- a silicide layer formed on the active regions;
- a polysilicon gate line electrically connecting the active regions to the polysilicon pads and configured to at least pass through the active regions a plurality of times;
- device isolation regions formed in the semiconductor substrate;
- and
- a plurality of gate oxide patterns on the N-well regions,
- wherein the poly gate line is formed on the gate oxide patterns, the N-well regions are formed between the device isolation regions and the active regions comprise source regions and drain regions alternately disposed on both sides of the poly gate line, and
- wherein the silicide layer is formed on the polysilicon gate line and the active regions.
Dependencies are inferred from the claim text.