US 7,888,203 B2Granted

Methods of making nonvolatile memory devices

AssigneeSamsung Electronics Co., Ltd.

InventorsChang-Hyun Lee, Jung-Dal Choi

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Abstract

Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

Claims8

Dependent claims

A method of making a nonvolatile memory device, the method comprising:

forming a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor where each has a channel region and source/drain regions in a substrate;
injecting first impurity ions into edge portions of the channel regions in the substrate to form first impurity layers around boundaries between the channel regions and the source/drain regions of each of the string selection transistor, the memory cell transistors, and the ground selection transistor, the first impurity layers having an opposite conductivity relative to the source/drain regions of each of the string selection transistor, the memory cell transistors, and the ground selection transistor;
and
injecting second impurity ions, which are the same conductivity type as the first impurity ions, into an edge portion of the channel regions of each of the string selection transistor and the ground selection transistor to form second impurity layers at boundaries between the channel region and the drain region of the string selection transistor and between the channel region and the source region of the ground selection transistor,
wherein injecting second impurity ions comprises:
forming an ion implantation mask on the substrate that exposes portions of the drain region of the string selection transistor and the source region of the ground selection transistor;
injecting the second impurity ions into the exposed portions of the drain region of the string selection transistor and the source region of the ground selection transistor, and
an interval between the memory cell transistors is L1, a height of the memory cell transistors from the substrate is L2, and the first and second impurity ions are injected at an incident angle θ1 defined by θ1≧tan−1(L2/L1).

5 more elements

A method of making a nonvolatile memory device, the method comprising:

forming a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor where each has a channel region and source/drain regions in a substrate;
and
forming impurity layers in the substrate around boundaries between the channel regions and the source/drain regions of each of the string selection transistor, the memory cell transistors, and the ground selection transistor while preventing formation of impurity layers at boundaries between the channel region and the drain region of a first one of memory cell transistors that is closest to the string selection transistor and between the channel region and the source region of a second one of the memory cell transistors that is closest to the ground selection transistor, wherein an interval between the memory cell transistors is L1, a height of the memory cell transistors from the substrate is L2, and the impurity layers are formed by injecting impurity ions at an incident angle θ1 defined by θ1≧tan−1(L2/L1).

Dependencies are inferred from the claim text.

Facts

Application: 11/363,326Filed 27 Feb 2006
Priority: KR 10-2005-00281174 Apr 2005
Published: US 2006/0220098 A15 Oct 2006
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B
Electronic memory devices