Embedded memory in a CMOS circuit and methods of forming the same

A method of forming a memory circuit, the method comprising:

• forming a gate layer on a substrate;
• forming a dielectric layer over the gate layer;
• forming a via opening in the dielectric layer to expose the gate layer, wherein the via opening extends from an upper surface of the dielectric layer to the gate layer;
• forming a two-terminal memory element in the via opening, the two-terminal memory element comprising a diode and having a first electrode formed from the gate layer;
• forming a first metal layer directly on the upper surface of the dielectric layer, and wherein the two terminal memory element is formed between the gate layer and the first metal layer;
• and
• forming a CMOS transistor on the substrate for programming the two-terminal memory element, the CMOS transistor having a gate electrode formed from the gate layer deposited on the substrate.

A method of forming a memory circuit, the method comprising:

• forming a gate layer on a substrate;
• forming a dielectric layer over the gate layer;
• forming a plurality of via openings in the dielectric layer to expose the gate layer, wherein each via opening extends from an upper surface of the dielectric layer to the gate layer;
• forming a plurality of two-terminal memory elements on a substrate, each two-terminal memory element formed in a corresponding one of the via openings and comprising a diode, each two-terminal memory element further having a first electrode and a second electrode;
• forming a first metal layer directly on the upper surface of the dielectric layer, and wherein each two terminal memory element is formed between the gate layer and the first metal layer;
• and
• forming a CMOS transistor on the substrate for programming the two-terminal memory elements, the CMOS transistor having:
• a gate electrode formed from the gate layer deposited on the substrate;
• a drain region;
• and
• a drain contact that extends from the drain region to the first metal layer of the memory circuit;
• wherein the first electrode of each two-terminal memory element is formed from the gate layer used to form the gate electrode of the CMOS transistor and the second electrode of each two-terminal memory element is formed from the first metal layer of the memory circuit.

A method of forming a memory element comprising a diode, the method comprising:

• forming an isolation region in a substrate;
• forming a first conductor of a first conductivity type on the isolation region using a gate layer deposited on the substrate and employed as part of a gate electrode of a CMOS transistor for programming the memory element, the gate electrode being formed on the substrate;
• forming an interlayer dielectric layer over the substrate;
• forming a via opening in the interlayer dielectric layer to expose the first conductor, wherein the via opening extends from an upper surface of the interlayer dielectric layer to the first conductor;
• filling the via opening with polysilicon;
• doping an upper portion of the polysilicon filled via opening so as to form a polysilicon region of a second conductivity type;
• and
• forming a second conductor above the upper portion of the polysilicon filled via opening directly on the upper surface of the interlayer dielectric layer, and wherein the memory element is formed between the first conductor and the second conductor.

A method of forming a memory circuit, the method comprising:

• forming an isolation region in a substrate;
• forming a plurality of memory elements by:
• forming a plurality of first conductors of a first conductivity type on the isolation region using a gate layer deposited on the substrate and employed as part of a gate electrode of a CMOS transistor for programming the memory elements, the gate electrode being formed on the substrate;
• forming an interlayer dielectric layer over the substrate;
• forming a plurality of via openings in the interlayer dielectric layer to expose each first conductor, wherein each via opening extends from an upper surface of the interlayer dielectric to a corresponding one of the first conductors;
• and
• forming a plurality of diodes by:
• filling the via openings with polysilicon;
• doping an upper portion of the polysilicon filled via openings so as to form a polysilicon region of a second conductivity type in each polysilicon filled via opening;
• and
• forming a second conductor directly on the upper surface of the interlayer dielectric layer, and wherein each memory element is formed between a corresponding one of the first conductors and the second conductor.