A design structure for an integrated circuit, said design structure comprising at least layout parameters, test pattern and other testing information, and manufacturing line routing information, said design structure being embodied in a non-transitory storage medium and readable by a machine that processes said design structure to produce said integrated circuit, said integrated circuit comprising:
- a chip said design structure;
- multiple first blocks on said chip, said multiple first blocks comprising functional devices;
- and
- multiple second blocks on said chip adjacent to said multiple first blocks, each of said second blocks comprising at least one decoupling capacitor and having a predetermined configuration so that a predetermined combined total decoupling capacitance is exhibited said multiple second blocks and further so that polysilicon perimeter density is approximately uniform across said chip, said polysilicon perimeter density being the sum of the perimeter of polysilicon shapes in a defined region of said integrated circuit divided by the area of said defined region.