Semiconductor integrated circuit device having standard cell including resistance element
AssigneeNEC Electronics Corporation
InventorKyoka Tatsumi
Life of this patent
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Abstract
A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell.
Claims10
A semiconductor integrated circuit device, comprising:
- a first power supply wiring which receives a first voltage supply;
- a second power supply wiring, which receives a second voltage supply and is laid in parallel to the first power supply wiring;
- a plurality of standard cells provided in a substantially rectangular area having two sides that are a part of the first power supply wiring and a part of the second power supply wiring;
- and
- at least one transistor resistance area provided in the rectangular area, wherein each of the standard cells includes:
- a first well of a first conductivity provided along the first power supply wiring;
- a second well of a second conductivity provided along the second power supply wiring and between the first well and the second power supply wiring;
- a first-conductivity MOS transistor provided in the second well;
- and
- a second-conductivity MOS transistor provided in the first well, wherein the transistor resistance area includes:
- a third well of the first or second conductivity, having a substantially rectangular shape including two sides that are a portion of the first power supply wiring and a portion of the second power supply wiring;
- and
- a plurality of MOS transistor resistances each having a conductivity opposite to that of the third well, and
- wherein the plurality of MOS transistor resistances are arranged so that a number of MOS transistor resistances among the plurality of MOS transistor resistances are connected to each other serially, in parallel, or in a combination of serial and parallel connections between the first-conductivity MOS transistor and the second-conductivity MOS transistor.
Dependencies are inferred from the claim text.