SOI radio frequency switch with reduced signal distortion

A method of operating a semiconductor device comprising:

• providing a semiconductor device including:
• a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer, a buried insulator layer, and a bottom semiconductor layer;
• at least one field effect transistor located on said top semiconductor layer;
• a shallow trench isolation structure laterally abutting said at least one field effect transistor;
• a degenerately doped semiconductor region embedded in the bottom semiconductor layer and abutting the buried insulator layer and having a doping of the same conductivity type as the bottom semiconductor layer, the doped semiconductor region located in regions not below said at least one field effect transistor;
• and
• at least one conductive via extending from a top surface of a middle-of-line (MOL) dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of said doped semiconductor region;
• applying a radio frequency (RF) signal to said at least one field effect transistor, wherein an induced charge layer is formed directly underneath said buried insulator layer;
• and
• electrically biasing said doped semiconductor region and said at least one conductive via, wherein an entirety of said induced charge layer is in depletion mode through an entirety of a cycle of said RF signal.

A semiconductor structure comprising:

• a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer, a buried insulator layer, and a bottom semiconductor layer having a doping concentration;
• at least one field effect transistor located on said top semiconductor layer;
• a shallow trench isolation structure laterally abutting said at least one field effect transistor;
• a doped semiconductor region embedded in said bottom semiconductor layer and abutting said buried insulator layer and having a doping of the same conductivity type as said bottom semiconductor layer, said doped semiconductor region excluded from regions beneath said at least one field effect transistor, and said doped semiconductor region having a doping concentration significantly greater than said doping concentration of said bottom semiconductor layer;
• and
• at least one conductive via extending from a top surface of a middle-of-line (MOL) dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, said buried insulator layer, and to a top surface of said doped semiconductor region, wherein said at least one conductive via comprises a contact via of unitary construction and laterally surrounding an entirety of said at least one field effect transistor.

A machine readable storage medium embodying a design structure, said design structure comprising:

• a first data representing a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer, a buried insulator layer, and a bottom semiconductor layer having a doping concentration;
• a second data representing at least one field effect transistor located on said top semiconductor layer;
• a third data representing a shallow trench isolation structure laterally abutting said at least one field effect transistor;
• a fourth data representing a doped semiconductor region embedded in said bottom semiconductor layer and abutting said buried insulator layer and having a doping of the same conductivity type as said bottom semiconductor layer, said doped semiconductor region excluded from regions beneath said at least one field effect transistor, and said doped semiconductor region having a doping concentration significantly greater than said doping concentration of said bottom semiconductor layer;
• and
• a fifth data representing at least one conductive via extending from a top surface of a middle-of-line (MOL) dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, said buried insulator layer, and to a top surface of said doped semiconductor region, wherein said at least one conductive via comprises a contact via of unitary construction and laterally surrounding an entirety of said at least one field effect transistor.