Semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprising:

• a plurality of cell transistors, each of the cell transistors including a silicon pillar formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, and first and second diffusion layers provided respectively at lower and upper parts of the silicon pillar;
• a first interlayer insulating layer covering the cell transistors;
• a plurality of storage node contacts each buried in the first interlayer insulating layer, the plurality of the storage node contacts in contact with the second diffusion layer of an associated one of the cell transistors;
• a second interlayer insulating layer provided over the first interlayer insulating layer with a cavity therebetween, the cavity being substantially free from being filled with an insulating material to maintain an air gap between the first and second interlayer insulating layers;
• and
• a plurality of capacitors each including a lower portion, an upper portion, and a middle portion, the lower portion of each of the capacitors embedded in the first interlayer insulating layer and in contact with an associated one of the second diffusion layers of the cell transistors, the upper portion of each of the capacitors embedded in the second interlayer insulating layer, and the middle portion of each of the capacitors disposed in the air gap.

A device comprising:

• a memory cell area comprising:
• a plurality of cell transistors arranged in a line, each of the cell transistors including a silicon pillar protruding from a substrate and first and second diffusion regions provided respectively at lower and upper portions of the silicon pillar, the silicon pillar including a middle portion between the lower and upper portions which functions as a channel region,
• an interlayer insulating layer covering the cell transistors, and
• a plurality of storage elements each provided over the interlayer insulating layer and electrically connected at one end to the second diffusion region of the associated one of the cell transistors;
• and
• a word line connection region provided adjacent to the memory cell area;
• the memory cell area further comprising:
• a word line extended along the cell transistors to include a plurality of gate electrode portions, each of the gate electrode portions facing a channel region of the silicon pillar of an associated one of the cell transistors with an intervention of an insulating film therebetween, the word line further extended to a word line connecting area to provide an extended portion in the word line connection region, and
• an auxiliary word line provided in the interlayer insulating layer and substantially parallel to the word line with a separation therefrom by the interlayer insulating layer, the auxiliary word line extends to the word line connecting area to provide an elongated portion in the word line connection region;
• and
• the word line connection region comprising a contact plug connecting the extended portion of the word line and the elongated portion of the auxiliary word line with each other so that the auxiliary word line is electrically connected to the word line.