Semiconductor memory cell and semiconductor memory array using the same
AssigneePanasonic Corporation
InventorYoshihisa Kato
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Abstract
A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate electrode of the first FET and a second gate electrode of the second FET are formed on the dielectric film, and a drain electrode and a source electrode are formed on the semiconductor film. Under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween, and the ends of the semiconductor film that forms the channel are located inwardly of the ends of the back-gate electrode.
Claims12
A semiconductor memory cell comprising a memory element including a first field effect transistor and a selection switch including a second field effect transistor, the memory element and the selection switch being connected in series,
- wherein a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first field effect transistor and the second field effect transistor;
- a first gate electrode of the first field effect transistor and a second gate electrode of the second field effect transistor are formed on the dielectric film;
- on the semiconductor film, a drain electrode is formed outwardly of the first gate electrode, and a source electrode is formed outwardly of the second gate electrode;
- under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween;
- and
- ends of the semiconductor film that forms the channel are located inwardly of ends of the back-gate electrode.
Dependencies are inferred from the claim text.