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US 7,842,570 B2Granted
Semiconductor memory devices and methods of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsAlbert Fayrushin, Byung-Yong Choi, Choong-Ho Lee
Life of this patent
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Abstract
In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.
Claims15
A method of manufacturing a semiconductor memory device, comprising:
- forming a tunnel insulation layer on a substrate;
- forming a floating gate having a substantially uniform thickness on the tunnel insulation layer;
- forming a dielectric layer on the floating gate;
- forming a control gate on the dielectric layer;
- forming a preliminary floating gate pattern on the tunnel insulation layer;
- forming an etch stop layer pattern on the preliminary floating gate pattern;
- forming an isolation layer in the substrate adjacent an active region in the substrate, and
- removing a portion of the isolation layer until a top surface of the isolation layer has a height substantially the same as a height of a lowermost portion of the etch stop layer pattern.
5 more elements
A method of manufacturing a semiconductor memory device, comprising:
- forming a tunnel insulation layer on a substrate;
- forming a floating gate having a substantially uniform thickness on the tunnel insulation layer, wherein forming the floating gate comprises forming a preliminary floating gate pattern on the tunnel insulation layer and removing a portion of the preliminary floating gate pattern by an isotropic etching process;
- forming a dielectric layer on the floating gate;
- forming a control gate on the dielectric layer;
- forming an etch stop later pattern on the preliminary floating gate pattern before removing the portion of the preliminary floating gate pattern;
- forming an isolation layer in the substrate adjacent an active region in the substrate, wherein forming the preliminary floating gate pattern comprises forming a preliminary floating gate layer on the active region and on the isolation layer;
- forming an etch stop layer on the preliminary floating gate layer;
- forming a sacrificial layer on the etch stop layer;
- removing portions of the sacrificial layer, the etch stop layer and the preliminary floating gate layer to expose the isolation layer and to form a sacrificial layer pattern and the preliminary floating gate pattern on the etch stop layer pattern;
- removing the sacrificial layer pattern to expose the etch stop layer pattern;
- and
- removing a portion of the isolation layer until a top surface of the isolation layer has a height substantially the same as a height of a lowermost portion of the preliminary floating gate pattern.
9 more elements
A method of manufacturing a semiconductor memory device, comprising:
- forming a tunnel insulation layer on a substrate;
- forming a floating gate having a substantially uniform thickness on the tunnel insulation layer, wherein forming the floating gate comprises forming a preliminary floating gate pattern on the tunnel insulation layer and removing a portion of the preliminary floating gate pattern by an isotropic etching process;
- forming a dielectric layer on the floating gate;
- forming a control gate on the dielectric layer;
- forming an etch stop layer pattern on the preliminary floating gate pattern before removing the portion of the preliminary floating gate pattern;
- forming an isolation layer in the substrate adjacent an active region in the substrate, wherein forming the preliminary floating gate pattern comprises forming a preliminary floating gate layer on the active region and on the isolation layer;
- forming an etch stop layer on the preliminary floating gate layer;
- forming a sacrificial layer on the etch stop layer;
- removing portions of the sacrificial layer, the etch stop layer and the preliminary floating gate layer to expose the isolation layer and to form a sacrificial layer pattern and the preliminary floating gate pattern on the etch stop layer pattern;
- and
- forming a silicon oxide layer on a sidewall of the trench, wherein forming the opening comprises removing a portion of the silicon oxide layer.
8 more elements
A method of manufacturing a semiconductor memory device, comprising:
- forming an isolation layer in a substrate adjacent an active region in the substrate;
- forming a tunnel insulation layer on the active region;
- forming a preliminary floating gate layer on the tunnel insulation layer and on the isolation layer;
- forming an etch stop layer on the preliminary floating gate layer;
- forming a sacrificial layer on the etch stop layer;
- removing portions of the sacrificial layer, the etch stop layer and the preliminary floating gate layer to expose the isolation layer and to form a preliminary floating gate pattern on the tunnel insulation layer;
- isotropically etching the preliminary floating gate pattern to form a floating gate having a substantially uniform thickness;
- removing the etch stop layer;
- forming a dielectric layer on the floating gate;
- and
- forming a control gate on the dielectric layer.
8 more elements
Dependencies are inferred from the claim text.