Cross correlation circuits and methods

A communication system comprising:

• a wireless receiver, the wireless receiver receiving a signal including a first sequence of data values and converting the first sequence of data values into a sequence of digital data values, the wireless receiver further comprising a plurality of cross correlators that each receive the digital data values and cross correlate the digital data values with a corresponding plurality of different binary reference patterns,
• wherein if the first sequence of data values correlates with one of said plurality of binary reference patterns, one of said cross correlators generates a peak, and wherein each cross correlator of the plurality of cross correlators comprise:
• a first cross correlator stage comprising:
• a memory coupled to receive the digital data values;
• a register for storing a first plurality of binary reference pattern values;
• and
• a plurality of XOR gates, wherein each XOR gate has a first input coupled to receive a digital data value and a second input coupled to receive a binary reference pattern value;
• and
• a summing network coupled to the plurality of XOR gates;
• and
• a second cross correlator stage coupled the summing network, wherein the second cross correlator stage comprises N binary reference pattern values and a plurality of single cycle delays, and wherein the first cross correlator stage comprises M binary reference pattern values and implements N cycle delays, wherein N is a first number and M is a second number.

A communication system comprising:

• a wireless receiver, the wireless receiver receiving a signal including a first sequence of data values and converting the first sequence of data values into a sequence of digital data values, the wireless receiver further comprising a plurality of cross correlators that each receive the digital data values and cross correlate the digital data values with a corresponding plurality of different binary reference patterns,
• wherein if the first sequence of data values correlates with one of said plurality of binary reference patterns, one of said cross correlators generates a peak, and
• wherein each cross correlator of the plurality of cross correlators comprise a first cross correlator stage comprising:
• a memory coupled to receive the digital data values;
• a register for storing a first plurality of binary reference pattern values;
• and
• a plurality of XOR gates, wherein each XOR gate has a first input coupled to receive a digital data value and a second input coupled to receive a binary reference pattern value, and
• wherein rows of said memory are successively coupled to a first plurality of XOR gate inputs and the plurality of reference values are coupled to a second plurality of XOR gate inputs, and wherein said shift register is shifted after all the rows in said memory have been processed.

A communication system comprising:

• a wireless receiver, the wireless receiver receiving a signal including a first sequence of data values and converting the first sequence of data values into a sequence of digital data values, the wireless receiver further comprising a plurality of cross correlators that each receive the digital data values and cross correlate the digital data values with a corresponding plurality of different binary reference patterns,
• wherein if the first sequence of data values correlates with one of said plurality of binary reference patterns, one of said cross correlators generates a peak, and
• wherein each cross correlator of the plurality of cross correlators comprise a first cross correlator stage comprising:
• a memory coupled to receive the digital data values;
• a register for storing a first plurality of binary reference pattern values;
• and
• a plurality of XOR gates, wherein each XOR gate has a first input coupled to receive a digital data value and a second input coupled to receive a binary reference pattern value, and
• wherein the memory further comprises a row control counter clocked at a first frequency and a column control counter clocked at a frequency of 1/Mth the first frequency, wherein M is a number.

A cross correlator for use in a communication system comprising:

• a memory for receiving and storing digital data values;
• one or more data storage elements for storing reference pattern values, wherein the data storage elements comprise one or more shift registers;
• one or more logic circuits for combining the stored digital data values with the stored reference pattern values;
• and
• one or more summing networks coupled to the logic circuits;
• and
• a cross correlator stage coupled the one or more summing networks,
• wherein the cross correlator stage comprises N binary reference pattern values and a plurality of single cycle delays, and
• wherein the data storage elements store M binary reference pattern values and are shifted every N cycles, wherein N is a first number and M is a second number.

A cross correlator for use in a communication system comprising:

• a memory for receiving and storing digital data values;
• one or more data storage elements for storing reference pattern values;
• one or more logic circuits for combining the stored digital data values with the stored reference pattern values;
• and
• one or more summing networks coupled to the logic circuits,
• wherein said memory comprises columns and rows, and wherein the logic circuits each comprise a plurality of XOR gates, and wherein the rows of said memory are successively coupled to a first plurality of XOR gate inputs and the plurality of reference pattern values are coupled to a second plurality of XOR gate inputs, and wherein said reference pattern values are reconfigured after all the rows in said memory have been processed.

A cross correlator for use in a communication system comprising:

• a memory for receiving and storing digital data values;
• one or more data storage elements for storing reference pattern values;
• one or more logic circuits for combining the stored digital data values with the stored reference pattern values;
• and
• one or more summing networks coupled to the logic circuits,
• wherein the memory further comprises a row control counter clocked at a first frequency and a column control counter clocked at a second frequency that is an integer fraction of the first frequency.

A cross correlation method comprising:

• sequentially storing digital data values in a memory;
• coupling the digital data values stored in said memory to a plurality of first inputs of a plurality of programmable inverter stages;
• coupling a different first reference pattern to a second input of each of the plurality of programmable inverter stages, wherein each programmable inverter stage generates a plurality of outputs;
• adding the outputs of each of the programmable inverter stages;
• and
• correlating each added output with a different second reference pattern, wherein each second reference pattern comprises N binary reference pattern values, and wherein each first reference pattern comprises M binary reference pattern values, wherein N is a first number and M is a second number.

A cross correlation method comprising:

• sequentially storing digital data values in a memory;
• coupling the digital data values stored in said memory to a plurality of first inputs of a plurality of programmable inverter stages;
• coupling a different first reference pattern to a second input of each of the plurality of programmable inverter stages, wherein each programmable inverter stage generates a plurality of outputs;
• and
• adding the outputs of each of the programmable inverter stages,
• wherein the memory receives the digital data values at a first frequency and wherein each first reference pattern received at the second input of each of the plurality of programmable inverter stages is reconfigured at a second frequency that is an integer fraction of the first frequency.