US 7,804,140 B2Granted

Field effect transistor with reduced shallow trench isolation induced leakage current

AssigneeInternational Business Machines Corporation

InventorsLeland Chang, Anthony I. Chou, Shreesh Narasimha, Jeffrey W. Sleight

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Abstract

Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.

Claims17

Dependent claims

A semiconductor structure comprising:

a semiconductor portion located in a semiconductor substrate, said semiconductor portion having a first lengthwise sidewall, a second lengthwise sidewall, a first widthwise sidewall, and a second widthwise sidewall, and including a body region, a source region abutting said body region, and a drain region abutting said body region and disjoined from said source region, wherein said body region has a same composition throughout;
a gate dielectric in direct contact with an upper surface of said body region;
a shallow trench isolation structure located in said semiconductor substrate and laterally surrounding and abutting said semiconductor portion, wherein said source region laterally abuts said first widthwise sidewall, said drain region laterally abuts said second widthwise sidewall, and said source region and said drain region are separated from said first and second sidewalls by said body region, and wherein said body region is in direct contact with sidewalls of said shallow trench isolation structure;
and
a gate electrode overlying an edge of said source region and an edge of said drain region, wherein an underlying semiconductor layer is located directly beneath said body region and a bottom surface of said shallow trench isolation structure, said entirety of said body region and said underlying semiconductor layer have said same composition throughout and are epitaxially aligned to each other.

2 more elements

A semiconductor structure comprising:

a semiconductor portion located in a semiconductor substrate and including a body region, a source region abutting said body region, and a drain region abutting said body region and disjoined from said source region, wherein said body region has a same composition throughout;
a gate dielectric in direct contact with an upper surface of said body region;
a shallow trench isolation structure located in said semiconductor substrate and laterally surrounding and abutting said semiconductor portion, wherein said source region and said drain region are separated from said shallow trench isolation structure by said body region, and wherein said body region is in direct contact with sidewalls of said shallow trench isolation structure;
and
a gate electrode overlying an edge of said source region and an edge of said drain region, wherein an underlying semiconductor layer is located directly beneath said body region and a bottom surface of said shallow trench isolation structure, said entirety of said body region and said underlying semiconductor layer have said same composition throughout and are epitaxially aligned to each other.

2 more elements

A method of forming a semiconductor structure comprising:

providing a semiconductor portion having a first lengthwise sidewall, a second lengthwise sidewall, a first widthwise sidewall, and a second widthwise sidewall in a semiconductor substrate, wherein each of said first and second lengthwise sidewalls is directly adjoined to said first widthwise sidewall and said second widthwise sidewall;
forming a gate dielectric directly on an upper surface of a middle portion of said semiconductor portion;
forming a gate electrode on said gate dielectric, wherein said gate electrode overlies said first and second widthwise sidewalls and said middle portion of said semiconductor portion, wherein said middle portion is located between said first and second widthwise sidewalls;
and
forming a source region and a drain region within said semiconductor portion, wherein said source region is formed on one side of said middle portion and said drain region is formed on another side of said middle portion, and wherein each of said source region and said drain region is disjoined from said first and second lengthwise sidewalls, wherein an entirety of said middle portion has a same composition, and wherein said middle portion is in direct contact with sidewalls of said shallow trench isolation structure after said forming of said source region and said drain region, and said middle portion is an unimplanted semiconductor region in said semiconductor substrate, and said semiconductor substrate further comprises an underlying semiconductor layer located directly beneath said middle portion and a bottom surface of a shallow trench isolation structure, wherein said entirety of said middle portion and said underlying semiconductor layer have said same composition throughout and are epitaxially aligned to each other after formation of said source region and said drain region.

2 more elements

Dependencies are inferred from the claim text.