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US 7,804,125 B2Granted
System and method for reducing process-induced charging
AssigneeSpansion LLC
InventorsAshot Melik Martirosian, Zhizheng Liu, Mark Randolph
Life of this patent
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Abstract
A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
Claims20
A semiconductor device comprising:
- a substrate;
- a memory cell formed on the substrate;
- and
- a contact to the substrate, where the substrate includes an area that includes a source region or a drain region, where the contact is located outside the area that includes the source region or the drain region, and where the contact is formed into the substrate at a depth ranging from about 50 Å to about 200 Å.
1 more element
A device comprising:
- a substrate;
- a source region formed in the substrate;
- a drain region formed in the substrate;
- an interlayer dielectric covering the source region and the drain region;
- and
- at least one contact formed through the interlayer dielectric into the substrate away from the source region and the drain region.
3 more elements
A semiconductor device comprising:
- a substrate;
- a source region and a drain region;
- a first dielectric layer;
- a charge storage layer;
- a second dielectric layer;
- a conductive layer;
- and
- a contact having a width ranging from about 250 Å to about 1000 Å and formed into the substrate at a depth ranging from about 50 Å to about 200 Å, where the contact is formed away from the source region and away from the drain region, and where the contact is to raise a potential of the substrate during etching performed subsequent to formation of the contact and reduce generation of electron-hole pairs in regions in the substrate adjacent the source region and the drain region during an etching process used to form the semiconductor device.
5 more elements
A semiconductor device comprising:
- a substrate;
- a memory cell formed on the substrate, the memory cell comprising:
- a source region;
- a drain region;
- a first dielectric layer;
- a charge storage layer comprising at least one of a silicon nitride, an oxide, or polysilicon, where the charge storage layer has a thickness ranging from about 60 Å to about 90 Å;
- a second dielectric layer;
- and
- a conductive layer;
- and
- a contact to the substrate, where the contact does not contact either the source region or the drain region, and where the contact is to raise a potential of the substrate during etching performed subsequent to formation of the contact.
8 more elements
Dependencies are inferred from the claim text.