Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory

A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a semiconductor body in direct contact with an insulating layer, the semiconductor body including a source, a drain, and a channel between the source and the drain;
• a control gate electrode;
• a floating gate electrode in direct contact with the insulating layer, the floating gate electrode juxtaposed with the channel of the semiconductor body, and the floating gate electrode disposed between the control gate electrode and the insulating layer;
• a first dielectric layer disposed between the channel of the semiconductor body and the floating gate electrode;
• and
• a second dielectric layer disposed between the control gate electrode and the floating gate electrode, the second dielectric layer in contact with the semiconductor body.