Method of joining a plurality of reticles for use in producing a semiconductor layout pattern, a computerized system for implementing such a method and a semiconductor mask arrangement produced by implementing such a method

Abstract

A method for joining a plurality of reticles is used for producing a semiconductor layout pattern, so that the reticles will collectively map a circuit arrangement on a semiconductor substrate. A plurality of matching patterns is provided that are each geometrically linked to a respective particular reticle and through detecting pairwise correspondence among the matching patterns likewise correspondence among the associated reticles is ascertained. In particular, the method has bulk sub-reticles and peripheral sub-reticles, and a first matching pattern associates to a peripheral sub-reticle that abuts a bulk sub-reticle and a second matching pattern to the bulk sub-reticle at such distance therefrom that fitting of the peripheral sub-reticle between the second matching pattern and the bulk sub-reticle allows matching of the first and second matching patterns. The bulk sub-reticles are used to constitute an array of sub-reticles.

Dependencies are inferred from the claim text.