US 7,786,505 B1Granted

Reduction of charge leakage from a thyristor-based memory cell

AssigneeT-RAM Semiconductor, Inc.

InventorsKevin J. Yang, Hyun-Jin Cho

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Abstract

Formation of a thyristor-based memory cell is described. A first gate dielectric of the storage element is formed over a base region thereof located in a silicon layer. A transistor is coupled to the storage element via a cathode region located in the silicon layer. The transistor has a gate electrode formed over a second gate dielectric. A spacer is formed at least in part along a sidewall of the gate electrode facing a gate electrode of the storage element. A shallow implant region is formed in the silicon layer responsive at least in part to the spacer. The spacer offsets the shallow implant region from the sidewall. A portion of the shallow implant region is for an extension region. The first gate dielectric and the second gate dielectric are formed at least in part by deposition of a dielectric material.

Claims10

Dependent claims

A thyristor-based memory cell, comprising:

a thyristor-based storage element, the thyristor-based storage element having a first gate electrode formed over a first gate dielectric, the first gate electrode having a first sidewall, the first gate dielectric formed over a base region of the thyristor-based storage element, the base region located in a silicon layer;
a transistor coupled to the thyristor-based storage element via a cathode region, the cathode region located in the silicon layer, the transistor having a second gate electrode formed over a second gate dielectric, the second gate electrode having a second sidewall, the second gate dielectric formed over a body region of the transistor, the body region located in the silicon layer;
a spacer formed at least in part along the second sidewall of the second gate electrode facing the first sidewall of the first gate electrode;
a shallow implant region formed in the silicon layer responsive at least in part to the spacer, the spacer offsetting the shallow implant region from the second sidewall, a portion of the shallow implant region being for an extension region;
in addition to being the cathode region for the thyristor-based storage element, the cathode region being for a source/drain type region of the transistor, wherein the cathode region includes the source/drain type region and another portion of the shallow implant region, the source/drain type region not including the extension region;
and
the first gate dielectric and the second gate dielectric formed at least in part by deposition of a dielectric material, the spacer formation being performed separately from formation of the first gate dielectric and the second gate dielectric;
wherein a portion of the spacer is formed by oxidation of a portion of the second gate electrode along the second sidewall thereof;
wherein the spacer extends under the second gate electrode responsive to the oxidation of the portion of the second gate electrode along the second sidewall thereof;
wherein the spacer extends to an upper surface of the silicon layer;
wherein a dielectric constant of the dielectric material is in a range of approximately 4 to 10;
and
wherein a dielectric material is selected from an oxynitride and an aluminum oxide.

10 more elements

A thyristor-based memory cell, comprising:

a thyristor-based storage element, the thyristor-based storage element having a first gate electrode formed over a first gate dielectric, the first gate electrode having a first sidewall, the first gate dielectric formed over a base region of the thyristor-based storage element, the base region located in a silicon layer;
a transistor coupled to the thyristor-based storage element via a cathode region, the cathode region located in the silicon layer, the transistor having a second gate electrode formed over a second gate dielectric, the second gate electrode having a second sidewall, the second gate dielectric formed over a body region of the transistor, the body region located in the silicon layer;
a spacer formed at least in part along the second sidewall of the second gate electrode facing the first sidewall of the first gate electrode;
a shallow implant region formed in the silicon layer responsive at least in part to the spacer, the spacer offsetting the shallow implant region from the second sidewall, a portion of the shallow implant region being for an extension region;
in addition to being the cathode region for the thyristor-based storage element, the cathode region being for a source/drain type region of the transistor, wherein the cathode region includes the source/drain type region and another portion of the shallow implant region, the source/drain type region not including the extension region;
and
the first gate dielectric and the second gate dielectric formed at least in part by deposition of a dielectric material, the spacer formation being performed separately from formation of the first gate dielectric and the second gate dielectric;
wherein a portion of the spacer is formed by oxidation of a portion of the second gate electrode along the second sidewall thereof;
wherein the spacer extends under the second gate electrode responsive to the oxidation of the portion of the second gate electrode along the second sidewall thereof;
wherein the spacer extends to an upper surface of the silicon layer;
and
wherein a dielectric constant of the dielectric material is in a range of approximately 10 to 20.

9 more elements

A thyristor-based memory cell, comprising:

a thyristor-based storage element, the thyristor-based storage element having a first gate electrode formed over a first gate dielectric, the first gate electrode having a first sidewall, the first gate dielectric formed over a base region of the thyristor-based storage element, the base region located in a silicon layer;
a transistor coupled to the thyristor-based storage element via a cathode region, the cathode region located in the silicon layer, the transistor having a second gate electrode formed over a second gate dielectric, the second gate electrode having a second sidewall, the second gate dielectric formed over a body region of the transistor, the body region located in the silicon layer;
a spacer formed at least in part along the second sidewall of the second gate electrode facing the first sidewall of the first gate electrode;
a shallow implant region formed in the silicon layer responsive at least in part to the spacer, the spacer offsetting the shallow implant region from the second sidewall, a portion of the shallow implant region being for an extension region;
in addition to being the cathode region for the thyristor-based storage element, the cathode region being for a source/drain type region of the transistor, wherein the cathode region includes the source/drain type region and another portion of the shallow implant region, the source/drain type region not including the extension region;
and
the first gate dielectric and the second gate dielectric formed at least in part by deposition of a dielectric material, the spacer formation being performed separately from formation of the first gate dielectric and the second gate dielectric;
wherein a portion of the spacer is formed by oxidation of a portion of the second gate electrode along the second sidewall thereof;
wherein the spacer extends under the second gate electrode responsive to the oxidation of the portion of the second gate electrode along the second sidewall thereof;
wherein the spacer extends to an upper surface of the silicon layer;
and
wherein a dielectric constant of the dielectric material is greater than at least approximately 20.

9 more elements

Dependencies are inferred from the claim text.