CMOS imaging facility and a modular array for use in such a facility

A CMOS imaging device comprising a pair of column conductors, an accumulator column disposed between the pair of column conductors, a left sharing circuit column coupled between the accumulator column and a left column conductor of the pair of column conductors, and a right sharing circuit column coupled between the accumulator column and a right column conductor of the pair of column conductors, wherein:

• the accumulator column comprises an odd sub-array of horizontal duplex accumulators and an even sub-array of horizontal duplex accumulators interleaved with the odd sub-array;
• the odd sub-array includes a first horizontal duplex accumulator;
• the even sub-array includes second and third horizontal duplex accumulators, the second and third horizontal duplex accumulators being different from one another;
• each horizontal duplex accumulator comprises a radiation-to-charge accumulator and left and right transfer transistors coupled to one another at a connection point, the radiation-to-charge accumulator being coupled to the connection point, the transfer transistors being for transferring a representation of a charge collected on the radiation-to-charge accumulator;
• the left sharing circuit column comprises plural vertical sharing circuits;
• the right sharing circuit column also comprises plural vertical sharing circuits;
• each vertical sharing circuit comprises a reset transistor fed by a reference voltage and a source follower transistor for feeding a select transistor that feeds said representation of a collected charge to a column conductor, the reset transistor being connected to the source follower transistor at a node;
• the plural vertical sharing circuits of the left sharing circuit column includes a first vertical sharing circuit;
• the plural vertical sharing circuits of the right sharing circuit column includes a second vertical sharing circuit;
• a left transfer transistor of the first horizontal duplex accumulator is coupled both to a left transfer transistor of the second horizontal duplex accumulator and to the node of the first vertical sharing circuit;
• and
• a right transfer transistor of the first horizontal duplex accumulator is coupled both to a right transfer transistor of the third horizontal duplex accumulator and to a node of the second vertical sharing circuit.