Flip-flop and pipelined analog-to-digital converter utilizing the same

A flip flop, comprising:

• a sense amplifier stage comprising:
• a first N type transistor comprising a gate receiving a clock signal and a source receiving a grounding signal;
• a second N type transistor comprising a gate receiving a first data signal and a source coupled to a drain of the first N type transistor;
• a third N type transistor comprising a gate receiving a second data signal and a source coupled to the drain of the first N type transistor;
• a fourth N type transistor comprising a gate receiving the grounding signal, a source receiving the grounding signal, and a drain coupled to a first node;
• a fifth N type transistor comprising a source coupled to a drain of the second N type transistor and a drain coupled to the first node;
• a sixth N type transistor comprising a gate receiving a reset signal, a source receiving the grounding signal, and a drain coupled to a second node;
• a seventh N type transistor comprising a source coupled to a drain of the third N type transistor and a drain coupled to the second node;
• a first P type transistor comprising a gate receiving the clock signal, a first terminal coupled to a gate of the fifth N type transistor, and a second terminal coupled to a gate of the seventh N type transistor;
• a second P type transistor comprising a gate receiving the clock signal and a drain coupled to the first node;
• a third P type transistor comprising a gate coupled to the gate of the fifth N type transistor and the second node, a drain coupled to the first node, and a source coupled to a source of the second P type transistor;
• a fourth P type transistor comprising a gate receiving the clock signal and a drain coupled to the second node;
• a fifth P type transistor comprising a gate coupled to the gate of the seventh N type transistor and the first node, a drain coupled to the second node, and a source coupled to a source of the fourth P type transistor;
• a sixth P type transistor comprising a gate receiving the grounding signal, a drain coupled to the source of the second P type transistor, and a source receiving a power signal;
• and
• a seventh P type transistor comprising a gate receiving the reset signal, a drain coupled to the source of the fourth P type transistor, and a source receiving the power signal;
• and
• a latch stage comprising:
• an eighth N type transistor comprising a gate coupled to the first node and a source receiving the grounding signal;
• a ninth N type transistor comprising a gate coupled to the second node and a source receiving the grounding signal;
• a tenth N type transistor comprising a gate receiving the second data signal and a source coupled to a drain of the eighth N type transistor;
• an eleventh N type transistor comprising a gate receiving the first data signal and a source coupled to a drain of the ninth N type transistor;
• a twelfth N type transistor comprising a gate receiving the clock signal, a source coupled to a drain of the tenth N type transistor, and a drain coupled to a third node;
• a thirteenth N type transistor comprising a gate receiving the clock signal, a source coupled to a drain of the eleventh N type transistor, and a drain coupled to a fourth node;
• an eighth P type transistor comprising a gate coupled to the first node, a source receiving the power signal, and a drain coupled to the third node;
• a ninth P type transistor comprising a gate coupled to the second node, a source receiving the power signal, and a drain coupled to the fourth node;
• and
• a latch unit coupled between the third and the fourth nodes.