Method, apparatus, and system providing multi-column shared readout for imagers

A CMOS imager, comprising:

• an array of pixels organized as a plurality of rows and columns;
• a plurality of first analog gain amplifiers, each coupled to a respective column;
• a plurality of sample-and-hold circuits, each coupled to a respective first analog gain amplifier;
• and
• a plurality of multi-column shared readout circuits, each selectively coupled to a respective group of sample-and-hold circuits, each multi-column shared readout circuit comprising:
• an analog black level correction clamp;
• a second analog gain amplifier coupled to the analog black level correction clamp;
• an analog-to-digital converter coupled to the second analog gain amplifier;
• a digital offset correction block coupled to the analog-to-digital converter;
• and
• a digital gain calibration block coupled to the digital offset correction block.

A processor system, comprising:

• a processor;
• an imaging device coupled to the processor, the imaging device comprising:
• an array of pixels organized as a plurality of rows and columns;
• a plurality of sample-and-hold circuits, each coupled to a respective column;
• and
• a plurality of multiplexers, each configured to selectively couple a group of sample-and-hold circuits to a respective multi-column shared readout circuit,
• wherein each multi-column shared readout circuit comprises:
• a multi-column analog gain amplifier;
• an analog-to-digital converter coupled to the analog gain amplifier;
• and
• a digital offset correction block coupled to the analog-to-digital converter.

A method of fabricating an imager, comprising the steps of:

• forming an array of pixels organized as rows and columns;
• forming a plurality of sample-and-hold circuits, each coupled to a respective column;
• and
• forming a plurality of multiplexers, each configured to selectively couple one of a group of adjacent columns to a respective multi-column shared readout circuit,
• wherein fabrication of the multi-column shared readout circuit comprises the steps of:
• forming a plurality of analog black level clamps, each coupled to a respective multiplexer;
• forming a plurality of multi-column analog gain amplifiers, each coupled to a respective analog black level clamp;
• forming a plurality of analog-to-digital converters, each coupled to a respective single-column gain amplifier;
• forming a plurality of digital offset correction blocks, each coupled to a respective analog-to-digital converter;
• forming a plurality of digital gain calibration blocks, each coupled to a respective digital offset correction block;
• and
• forming a digital line memory configured to receive and store pixel values output by each of the plurality of digital gain calibration block.