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US 7,746,337 B2Granted
Inverter circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsTatsuhisa Shimura, Takashi Kinoshita, Osamu Sengoku
Life of this patent
Estimating the term…
Abstract
An inverter circuit includes a first driving transformer, a second driving transformer, a power voltage circuit, a high-side FET connected to a secondary winding of the first driving transformer, a low-side FET connected to a secondary winding of the second driving transformer and an inverter transformer connected to a driving node between the high-side FET and the low-side FET. Thus, a direct current path does not exist between a gate of the high-side FET and the driving node, so that a gate voltage of the high-side FET is biased more to a negative polarity.
Claims21
An inverter circuit comprising:
- a first transformer having a primary winding to which a first control signal is applied;
- a second transformer having a primary winding to which a second control signal is applied;
- a power voltage circuit to generate a predetermined direct current voltage;
- a first field effect transistor electrically connected between the power voltage circuit and a driving node, the first field effect transistor having a gate connected to a secondary winding of the first transformer;
- a second field effect transistor electrically connected between the driving node and a ground, the second field effect transistor having a gate connected to a secondary winding of the second transformer;
- and
- a third transformer electrically connected to the driving node,
- wherein a voltage level applied to the gate of the first field effect transistor is maintained in a minus voltage level compared to a voltage level at the driving node during one cycle of the first control signal such that no direct current path exists between the gate of the first field effect transistor and the driving node.
5 more elements
An inverter circuit comprising:
- a first transformer having a primary winding to which a first control signal is applied;
- a second transformer having a primary winding to which a second control signal is applied;
- a power voltage circuit to generate a predetermined direct current voltage;
- a first field effect transistor electrically connected between the power voltage circuit and a driving node, the first field effect transistor having a gate connected to a secondary winding of the first transformer;
- a second field effect transistor electrically connected between the driving node and a ground, the second field effect transistor having a gate connected to a secondary winding of the second transformer;
- a third transformer electrically connected to the driving node;
- and
- a first resistor electrically connected to the gate of the first field effect transistor,
- wherein a first impedance converting circuit is connected between the secondary winding of the first transformer and the first resistor to reduce an impedance of the first resistor, which is viewed from the first transformer.
6 more elements
A liquid crystal display comprising:
- an inverter circuit to generate a power voltage;
- a backlight assembly to generate light in response to the power voltage from the inverter circuit;
- and
- a liquid crystal display panel that receives the light from the backlight assembly and image data to display an image,
- the inverter circuit comprises:
- a first transformer having a primary winding to which a first control signal is applied;
- a second transformer having a primary winding to which a second control signal is applied;
- a power voltage circuit to generate a predetermined direct current voltage;
- a first field effect transistor electrically connected between the power voltage circuit and a driving node, the first field effect transistor having a gate connected to a secondary winding of the first transformer;
- a second field effect transistor electrically connected between the driving node and a ground, the second field effect transistor having a gate connected to a secondary winding of the second transformer;
- and
- a third transformer electrically connected to the driving node,
- wherein a voltage level applied to the gate of the first field effect transistor is maintained in a minus voltage level compared to a voltage level at the driving node during one cycle of the first control signal such that no direct current path exists between the gate of the first field effect transistor and the driving node.
10 more elements
Dependencies are inferred from the claim text.