Liquid crystal display and shift register unit thereof

A liquid crystal display, comprising:

• a plurality of pixels;
• a plurality of data lines coupled to the pixels for transmitting an image data to the pixels;
• a plurality of odd-numbered scan signal lines and even-numbered scan signal lines, wherein the odd-numbered scan signal lines and the even-numbered scan signal lines are coupled to the pixels for transmitting a scan driving signal to the pixels;
• and a first scan driver and a second scan driver, wherein the first scan driver is for driving the odd-numbered scan signal lines, the second scan driver is for driving the even-numbered scan signal lines, the first scan driver and the second scan driver respectively comprises a plurality of level shift register units, each level shift register unit comprises:
• a first switch having a first input terminal, a first control terminal, and a first output terminal;
• a second switch having a second input terminal, a second control terminal, and a second output terminal, wherein the second control terminal is coupled to the first output terminal;
• and
• a level shift circuit coupled to the second control terminal and the second output terminal, the level shift circuit comprising:
• a first level shift module coupled to the second control terminal and the second output terminal;
• a second level shift module coupled to the second control terminal and the second output terminal;
• a third level shift module coupled to the second control terminal and the second output terminal;
• and
• a first control switch unit used for controlling the first level shift module, wherein the first control switch unit is controlled by an external signal, a first clock signal, and a second clock signal, when the external signal and the second clock signal are at an enabled level and when the first clock signal is at a non-enabled level, the first control switch unit enables the first level shift module;
• wherein, during a first time period, the first switch is enabled, the first input terminal receives an input signal converting the voltage of the second control terminal into a first voltage for turning on the second switch;
• wherein, during a second time period, the second control terminal is substantially maintained at the first voltage, the second input terminal receives the first clock signal, the second output terminal outputs the first clock signal to one of the odd-numbered scan signal lines or one of the even-numbered scan signal lines to form the scan driving signal;
• wherein, during a third time period, the first level shift module is enabled for converting the voltage of the second control terminal and the voltage of the second output terminal into a second voltage for turning off the second switch;
• wherein, after the third time period, the second level shift module and the third level shift module are alternately enabled to substantially maintain the voltage of the second control terminal and the voltage of the second output terminal at the second voltage.