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US 7,746,259 B2Granted
Switching circuitry
AssigneeFujitsu Semiconductor Limited
InventorsIan Juso Dedic, Darren Walker
Life of this patent
Estimating the term…
Abstract
A digital-to-analog converter, comprising: a first field-effect transistor; a second field-effect transistor; and adjusting means for adjusting a bulk voltage applied to at least one of the first and second field-effect transistors so as to tend to equalise respective switching delays of the transistors.
Claims31
A digital-to-analog converter, comprising:
- a first field-effect transistor;
- a second field-effect transistor;
- and
- adjusting means for adjusting a factor applied to one of the first and second field-effect transistors separately from the same factor applied to the other one of the first and second field-effect transistors so as to tend to equalise respective switching delays of the transistors, the factor being a bulk voltage and/or a gate voltage,
- wherein the adjusting means comprises measuring means operable to measure a predetermined property of each of the first and second field-effect transistors, the adjusting means being operable to adjust the bulk voltage applied to at least one of the first and second field-effect transistors so as to tend to equalise the measured property for both field-effect transistors.
2 more elements
Switching circuitry, operative repetitively in a series of switching phases, the circuitry comprising:
- at least one first field-effect transistor connected between a common node of the circuitry and a first node of the circuitry;
- at least one second field-effect transistor connected between said common node and a second node of the circuitry;
- switch control means connected with said first and second field-effect transistors and operable to cause the same number of field-effect transistors to change state in each said switching phase;
- and
- adjusting means for adjusting a factor applied to each, or each but one, of the field-effect transistors, so as to tend to equalise respective switching delays of the transistors, the factor being a bulk voltage and/or a gate voltage.
2 more elements
An input circuit comprising:
- an input node, at which an input signal is received;
- first and second circuit sections;
- a first field-effect transistor connected between the input node and said first circuit section;
- a second field-effect transistor connected between the input node and said second circuit section;
- control means connected with the first and second field-effect transistors for causing the first field-effect transistor to supply the input signal from the input node to the first circuit section in a first operating phase and for causing the second field-effect transistor to supply the input signal from the input node to the second circuit section in a second operating phase;
- and
- adjusting means for adjusting a factor applied to one or both of said first and second field-effect transistors so as to tend to equalise respective switching delays of the two transistors, the factor being a bulk voltage and/or a gate voltage.
4 more elements
An output circuit comprising:
- an output node, at which an output signal is received;
- first and second circuit sections;
- a first field-effect transistor connected between the output node and said first circuit section;
- a second field-effect transistor connected between the output node and said second circuit section;
- control means connected with the first and second field-effect transistors for causing the first field-effect transistor to supply the output signal from the first circuit section to the output node in a first operating phase and for causing the second field- effect transistor to supply the output signal from the second circuit section to the output node in a second operating phase;
- and
- adjusting means for adjusting a factor applied to one or both of said first and second field-effect transistors so as to tend to equalise respective switching delays of the two transistors, the factor being a bulk voltage and/or a gate voltage.
4 more elements
Dependencies are inferred from the claim text.