US 7,746,254 B2Granted

Sample and hold circuit, multiplying D/A converter having the same, and A/D converter having the same

AssigneeDenso Corporation

InventorsTetsuya Makihara, Masakiyo Horie

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Abstract

A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is α, a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is β, a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is γ, and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is η. α is substantially different from β. A total capacitance of a feedback capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.

Claims16

Dependent claims

A sample and hold circuit for sampling and holding an input voltage, the sample and hold circuit comprising:

an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals;
a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier;
a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance;
and
a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs,
wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α,
wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β,
wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ,
wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η,
wherein α is substantially different from β, and
wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.

8 more elements

A sample and hold circuit for sampling and holding an input voltage limited to a predetermined voltage range, the sample and hold circuit comprising:

an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals;
a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier;
a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance;
and
a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs,
wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α,
wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β,
wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ,
wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η,
wherein α+β is substantially equal to γ+η,
wherein α+η is substantially different from β+γ, and
wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.

9 more elements

A sample and hold circuit for sampling and holding an input voltage limited to a predetermined voltage range, the sample and hold circuit comprising:

an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals;
a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier;
a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance;
and
a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs,
wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α,
wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β,
wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ,
wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η,
wherein α+β is substantially equal to γ+η,
wherein α is substantially different from γ,
wherein β is substantially different from η, and
wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/318,201Filed 23 Dec 2008
Priority: JP 2007-33430826 Dec 2007
Published: US 2009/0167582 A12 Jul 2009
Granted: 29 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 27/026
Using a capacitive memory element: associated with an amplifier
H03M 1/129
Sampling or signal conditioning arrangements specially adapted for A/D converters: means for adapting the input signal to the range the converter…
H03M 1/0682
The original and additional components or elements being complementary to each other, e.g. CMOS: using a differential network structure, i.e.…
H03M 1/0695
By range overlap between successive stages or steps: using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or…

Family

US 2009/0167582 A1Pre-grant publication · published 2 Jul 2009
US 7,746,254 B2This patent

From the US filing history. Foreign family members aren’t listed.

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