High speed serializer/deserializer transmit architecture

A serializer circuit comprising:

• a pipe input stage that takes eight parallel data bits from a core and latches them using a core byte_clock;
• a serializer start block, wherein a tx_ff_ena signal is asserted by the core when the serializer should start, and wherein said tx_ff_ena signal from the core is synchronized to a full-rate clock tx_clk;
• a byte-select generator block that generates a byte-select signal that is synchronous to the full-rate clock and maximizes a setup/hold timing margin by loading data after said data has been resting in the pipe input stage for four tx_clk periods;
• a serializer output stage that loads the eight parallel data bits from the pipe input stage and then shifts them out serially, and repeats this operation every eight tx_clk periods.