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US 7,746,160 B1Granted
Substrate bias feedback scheme to reduce chip leakage power
AssigneeCypress Semiconductor Corporation
InventorsVijay Kumar Srinivasa Raghavan, Iulian Gradinariu
Life of this patent
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Abstract
Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.
Claims18
A substrate bias circuit, comprising:
- at least one baseline transistor having a plurality of terminals and a body;
- a current source that provides a current output to at least one terminal of the base line transistor;
- and
- a charge pump circuit that applies a reverse body bias to the body of the base line transistor, the reverse body bias varying in response to a difference between a reference current and a current through the baseline transistor, wherein the charge pump circuit includes at least one charge pump cell that generates the reverse body bias in response to a control clock signal, and an analog clock driver that varies the control clock signal in response to the difference between the reference current and the current through the baseline transistor.
1 more element
A substrate bias circuit, comprising:
- a charge pump that drives a substrate node to a reverse body bias voltage in response to at least one clock control signal;
- an analog clock driver that generates at least one output clock signal in response to a periodic input clock signal, and varies the amplitude of the output clock signal in response to a node voltage;
- and
- a bias amplifier that generates the node voltage in response to a leakage current through at least one base line transistor, the baseline transistor having a body that receives the reverse body bias voltage.
1 more element
A method, comprising:
- generating an analog control bias voltage in response to a comparison between a reference current and a leakage current flowing through at least one baseline transistor, the baseline transistor having a body the receives a reverse body bias voltage;
- and
- varying the reverse body bias voltage in response to the analog control bias voltage, wherein generating the analog control bias voltage includes generating a compare input voltage in response to a difference between the reference current and the leakage current through the baseline transistor, comparing the compare input voltage to a reference voltage to generate a compare result, and increasing or decreasing the reverse body bias voltage in response to the compare result.
Dependencies are inferred from the claim text.