Circuit and method for providing a fail-safe differential receiver

A fail-safe differential receiver circuit for use with a first differential input signal and a second differential input signal and at least one predetermined signal and a threshold voltage, the circuit comprising a first transistor coupled to the first differential input signal and a second transistor coupled to the second differential input signal for generating first and second differential signals that are based on the first and second differential input signals and have a differential voltage, a resistor coupled to a first current source for setting a threshold voltage, a third transistor coupled to the resistor and the first current source, a comparator coupled to the first, second, and third transistors for comparing the differential voltage to the threshold voltage and generating a comparison signal, and a fourth transistor and a fifth transistor coupled to the comparator for forming a directing circuit, the directing circuit selectively directing between the first and second differential signals and the at least one predetermined signal as a function of the value of the comparison signal from the comparator.

A method for providing a fail-safe differential receiver, the method comprising generating a peak voltage signal amplitude from first and second differential signals that are based on a first differential input signal and a second differential input signal, comparing the peak voltage signal amplitude to a threshold voltage to generate a comparison signal and providing the comparison signal to a directing circuit, the directing circuit selectively directing between the first and second differential signals and at least one predetermined signal as a function of the comparison signal.