US 7,746,145 B2 · Level shift circuit capable of preventing occurrence of malfunction when low power supply fluctuates, and semiconductor integrated circuit including the circuit

Abstract

A level shift circuit includes two high-voltage PMOS, two high-voltage NMOS, and two low-voltage NMOS transistors. The first high-voltage PMOS is connected between a high voltage and a second output terminal, having a gate connected to a first output terminal. The second high-voltage PMOS is connected between the high voltage and the first terminal, having a gate connected to the second terminal. The first high-voltage NMOS is connected to the second terminal, having a gate through which a second signal is input. The first low-voltage NMOS is connected between the first high-voltage N-channel MOS and a ground, having a gate through which the second signal is input. The second high-voltage NMOS is connected to the first terminal, having a gate through which a first signal is input. The second low-voltage NMOS is connected between the second N-channel MOS and the ground, having a gate through which the first signal is input.

Claims15

Dependent claims

A level shill circuit having a first power voltage and a second power voltage greater than the first power voltage, the level shill circuit comprising:

a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage;
a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal;
a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal;
a first high-withstand-voltage N-channel MOS transistor having a drain connected to the second output terminal and a source connected directly to a ground, and having a gate through which the second input signal is input;
a second high-withstand-voltage N-channel MOS depletion-type transistor connected to the first output terminal and having a gate through which the first input signal is input;
and
a second low-withstand-voltage N-channel MOS transistor connected between the second N-channel MOS depiction-type transistor and the ground and having a gate through which the first input signal is input,
wherein the second high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts.

5 more elements

A level shift circuit having a first power voltage and a second power voltage greater than the first power voltage, the level shift circuit comprising:

a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage;
a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal;
a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal;
a first high-withstand-voltage N-channel MOS depletion-type transistor connected to the second output terminal and having a gate through which the second input signal is input;
a first low-withstand-voltage N-channel MOS transistor connected between the first high-withstand-voltage N-channel MOS depletion-type transistor and a ground and having a gate through which the second input signal is input;
and
a second high-withstand-voltage N-channel MOS transistor having a drain connected to the first output terminal and a source connected directly to the ground, and having a gate through which the first input signal is input,
wherein the first high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts.

5 more elements

A semiconductor integrated circuit having a first power voltage and a second power voltage greater than the first power voltage, the semiconductor integrated circuit comprising:

a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage;
a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal;
a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal;
a first high-withstand-voltage N-channel MOS transistor having a drain connected to the second output terminal and a source connected directly to a ground, and having a gate through which the second input signal is input;
a second high-withstand-voltage N-channel MOS depletion-type transistor connected to the first output terminal and having a gate through which the first input signal is input;
and
a second low-withstand-voltage N-channel MOS transistor connected between the second N-channel MOS depletion-type transistor and the ground and having a gate through which the first input signal is input,
wherein the second high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts.

5 more elements

A semiconductor integrated circuit having a first power voltage and a second power voltage greater than the first power voltage, the semiconductor integrated circuit comprising:

a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage;
a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal;
a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal;
a first high-withstand-voltage N-channel MOS depletion-type transistor connected to the second output terminal and having a gate through which the second input signal is input;
a first low-withstand-voltage N-channel MOS transistor connected between the first high-withstand-voltage N-channel MOS depletion-type transistor and a ground and having a gate through which the second input signal is input;
and
a second high-withstand-voltage N-channel MOS transistor having a drain connected to the first output terminal and a source connected directly to the ground, and having a gate through which the first input signal is input;
wherein the first high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts.

5 more elements

Dependencies are inferred from the claim text.

Level shift circuit capable of preventing occurrence of malfunction when low power supply fluctuates, and semiconductor integrated circuit including the circuit

Life of this patent

Level shift circuit capable of preventing occurrence of malfunction when low power supply fluctuates, and semiconductor integrated circuit including the circuit

Life of this patent

Abstract

Claims15