Radiation hardened D-type flip flop

A radiation hardened D-type flip flop comprising:

• a master latch having a clock input, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs;
• and
• a slave latch having first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs,
• wherein the first data output and the first complementary data output of the master latch are connected respectively to the first data input and the first complementary data input of the slave latch,
• wherein the second data output and the second complementary data output of the master latch are connected respectively to the second data input and the second complementary data input of the slave latch, and
• wherein the master latch comprises:
• a first master latch half circuit having a clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output;
• and
• a second master latch half circuit identical to the first master latch half circuit and having a clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output,
• wherein
• the respective clock inputs of the first and second master latch half circuits are connected together in parallel,
• the respective first and second data inputs and first and second complementary data inputs of the first and second master latch half circuits are connected together in parallel,
• the data output and the complementary data output of the first master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second master latch half circuit, and
• the data output and the complementary data output of the second master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the first master latch half circuit.

A radiation hardened D-type flip flop comprising:

• a master latch having a clock input, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs;
• and
• a slave latch having first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs,
• wherein the first data output and the first complementary data output of the master latch are connected respectively to the first data input and the first complementary data input of the slave latch,
• wherein the second data output and the second complementary data output of the master latch are connected respectively to the second data input and the second complementary data input of the slave latch, and
• wherein the slave latch comprises:
• a first slave latch half circuit having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output;
• and
• a second slave latch half circuit identical to the first slave latch half circuit and having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output,
• wherein
• the first data input and the first complementary data input of the first slave latch half circuit are respective connected in parallel with the second data input and the second complementary data input of the second slave latch half circuit,
• the second data input and the second complementary data input of the first slave latch half circuit are respectively connected in parallel with the first data input and the first complementary data input of the second slave latch half circuit,
• the data output and the complementary data output of the first slave latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second slave latch half circuit, and
• the data output and the complementary data output of the second slave latch half circuit are connected respectively to the feedback input and complementary feedback input of the first slave latch half circuit.